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MK64FX512VLQ12 clocking problems

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MK64FX512VLQ12 clocking problems

‎04-29-2015 08:29 AM
521 Views
ad52655
Contributor II

I'm working on migrating from the K60 to the K64.  I am starting with the hello example from the independent project MQX 4.1 TWRK64F120.  On our board we're using an external 24 MHz oscillator with a 1 M ohm resistor in parallel connected to PTA18 (EXTAL)and PTA19 (XTAL).  I got the example going relatively quick with the 1M part (MK64FN1M0VLQ12).  But when trying to get it going in the 512 part (MK64FX512VLQ12), it completely freezes up in the clock management setup.  This causes the PLL to not be initialized correctly and the debugger won't connect until I enter ISP mode and erase all of the flash.  Are there any clocking differences between the 512 part and the 1 M part?  I'm using UVision 5 with the device set up for the 512 part.

Here's my initial and state machine settings from bsp_cm.c.  I got most of these values from setting the part up in KDS which works great but is bare metal and I need MQX.

/* Clock configuration 0 */

#define CPU_MCG_MODE_CONFIG_0                              (CPU_MCG_MODE_PEE | CPU_CLOCK_EXTERNAL_CRYSTAL_MASK | CPU_CLOCK_SLOW_MASK)  /* Clock generator mode */

#define CPU_CLOCK_VLP_CONFIG_0                             0U /* Very low power mode disabled */

#define CPU_MCG_C1_CONFIG_0                                0x28U /* MCG_C1 */

#define CPU_MCG_C2_CONFIG_0                                0x24U /* MCG_C2 */

#define CPU_MCG_C4_CONFIG_0                                0x00U /* MCG_C4 */

#define CPU_MCG_C5_CONFIG_0                                0x05U /* MCG_C5 */

#define CPU_MCG_C6_CONFIG_0                                0x46U /* MCG_C6 */

#define CPU_MCG_SC_CONFIG_0                                0x00U /* MCG_SC */

#define CPU_OSC_CR_CONFIG_0                                0xA0U /* OSC_CR */

#define CPU_SIM_SOPT1_CONFIG_0                             0x00000000UL /* SIM_SOPT1 */

#define CPU_SIM_SOPT2_CONFIG_0                             0x00010000UL /* SIM_SOPT2 */ //set to core/system clock out

#define CPU_SIM_CLKDIV1_CONFIG_0                           0x01140000UL /* SIM_CLKDIV1 */

/* MCG_C1: CLKS=0,IREFS=1,IRCLKEN=0,IREFSTEN=0 */

#define CPU_DEFAULT_FEI_MCG_C1                             0x04U     /* MCG_C1 value in FEI default state */

/* MCG_C2: LOCRE0=1 */

#define CPU_DEFAULT_FEI_MCG_C2                             0x80U     /* MCG_C2 value in FEI default state */

/* MCG_C4: DMX32=0,DRST_DRS=0 */

#define CPU_DEFAULT_FEI_MCG_C4                             0x00U     /* MCG_C4 value in FEI default state */

/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */

#define CPU_DEFAULT_FEI_MCG_C5                             0x00U     /* MCG_C5 value in FEI default state */

/* MCG_C6: LOLIE0=0,CME0=0,VDIV0=0 */

#define CPU_DEFAULT_FEI_MCG_C6                             0x00U     /* MCG_C6 value in FEI default state */

/* MCG_C6: VDIV0|=2 */

#define CPU_DEFAULT_FEI_MCG_SC                             0x02U     /* MCG_SC value in FEI default state */

/* OSC_CR: ERCLKEN=0,EREFSTEN=0 */

#define CPU_DEFAULT_FEI_OSC_CR                             0x00U     /* OSC_CR value in FEI default state */

/* MCG_C1: CLKS|=1,IREFS=1,IRCLKEN=0,IREFSTEN=0 */

#define CPU_DEFAULT_FBI_MCG_C1                             0x44U     /* MCG_C1 value in FBI default state */

/* MCG_C2: LOCRE0=1 */

#define CPU_DEFAULT_FBI_MCG_C2                             0x80U     /* MCG_C2 value in FBI default state */

/* MCG_C4: DMX32=0,DRST_DRS=0 */

#define CPU_DEFAULT_FBI_MCG_C4                             0x00U     /* MCG_C4 value in FBI default state */

/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */

#define CPU_DEFAULT_FBI_MCG_C5                             0x00U     /* MCG_C5 value in FBI default state */

/* MCG_C6: LOLIE0=0,CME0=0,VDIV0=0 */

#define CPU_DEFAULT_FBI_MCG_C6                             0x00U     /* MCG_C6 value in FBI default state */

/* MCG_C6: VDIV0|=2 */

#define CPU_DEFAULT_FBI_MCG_SC                             0x02U     /* MCG_SC value in FBI default state */

/* OSC_CR: ERCLKEN=0,EREFSTEN=0 */

#define CPU_DEFAULT_FBI_OSC_CR                             0x00U     /* OSC_CR value in FBI default state */

/* MCG_C1: CLKS|=1,IREFS=1,IRCLKEN=0,IREFSTEN=0 */

#define CPU_DEFAULT_BLPI_MCG_C1                            0x44U     /* MCG_C1 value in BLPI default state */

/* MCG_C2: LOCRE0=1,LP=1 */

#define CPU_DEFAULT_BLPI_MCG_C2                            0x82U     /* MCG_C2 value in BLPI default state */

/* MCG_C4:  */

#define CPU_DEFAULT_BLPI_MCG_C4                            0x00U     /* MCG_C4 value in BLPI default state */

/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */

#define CPU_DEFAULT_BLPI_MCG_C5                            0x00U     /* MCG_C5 value in BLPI default state */

/* MCG_C6: LOLIE0=0,CME0=0,VDIV0=0 */

#define CPU_DEFAULT_BLPI_MCG_C6                            0x00U     /* MCG_C6 value in BLPI default state */

/* MCG_C6: VDIV0|=2 */

#define CPU_DEFAULT_BLPI_MCG_SC                            0x02U     /* MCG_SC value in BLPI default state */

/* OSC_CR: ERCLKEN=0,EREFSTEN=0 */

#define CPU_DEFAULT_BLPI_OSC_CR                            0x00U     /* OSC_CR value in BLPI default state */

/* MCG_C1: CLKS=0,FRDIV|=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

#define CPU_DEFAULT_FEE_MCG_C1                             0x28U     /* MCG_C1 value in FEE default state */

/* MCG_C2: LOCRE0=1,RANGE|=2,EREFS=1 */

#define CPU_DEFAULT_FEE_MCG_C2                             0xA4U     /* MCG_C2 value in FEE default state */

/* MCG_C4: DMX32=0,DRST_DRS=0 */

#define CPU_DEFAULT_FEE_MCG_C4                             0x00U     /* MCG_C4 value in FEE default state */

/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */

#define CPU_DEFAULT_FEE_MCG_C5                             0x00U     /* MCG_C5 value in FEE default state */

/* MCG_C6: LOLIE0=0,CME0=0,VDIV0=0 */

#define CPU_DEFAULT_FEE_MCG_C6                             0x00U     /* MCG_C6 value in FEE default state */

/* MCG_C6: VDIV0|=2 */

#define CPU_DEFAULT_FEE_MCG_SC                             0x02U     /* MCG_SC value in FEE default state */

/* OSC_CR: ERCLKEN=0,EREFSTEN=0 */

#define CPU_DEFAULT_FEE_OSC_CR                             0x00U     /* OSC_CR value in FEE default state */

/* MCG_C1: CLKS|=2,FRDIV|=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

#define CPU_DEFAULT_FBE_MCG_C1                             0xA8U     /* MCG_C1 value in FBE default state */

/* MCG_C2: LOCRE0=1,RANGE|=2,EREFS=1 */

#define CPU_DEFAULT_FBE_MCG_C2                             0xA4U     /* MCG_C2 value in FBE default state */

/* MCG_C4: DMX32=0,DRST_DRS=0 */

#define CPU_DEFAULT_FBE_MCG_C4                             0x00U     /* MCG_C4 value in FBE default state */

/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */

#define CPU_DEFAULT_FBE_MCG_C5                             0x00U     /* MCG_C5 value in FBE default state */

/* MCG_C6: LOLIE0=0,CME0=0,VDIV0=0 */

#define CPU_DEFAULT_FBE_MCG_C6                             0x00U     /* MCG_C6 value in FBE default state */

/* MCG_C6: VDIV0|=2 */

#define CPU_DEFAULT_FBE_MCG_SC                             0x02U     /* MCG_SC value in FBE default state */

/* OSC_CR: ERCLKEN=0,EREFSTEN=0 */

#define CPU_DEFAULT_FBE_OSC_CR                             0x00U     /* OSC_CR value in FBE default state */

/* MCG_C1: CLKS|=1,FRDIV|=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

#define CPU_DEFAULT_BLPE_MCG_C1                            0x68U     /* MCG_C1 value in BLPE default state */

/* MCG_C2: LOCRE0=1,RANGE|=2,EREFS=1,LP=1 */

#define CPU_DEFAULT_BLPE_MCG_C2                            0xA6U     /* MCG_C2 value in BLPE default state */

/* MCG_C4:  */

#define CPU_DEFAULT_BLPE_MCG_C4                            0x00U     /* MCG_C4 value in BLPE default state */

/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */

#define CPU_DEFAULT_BLPE_MCG_C5                            0x00U     /* MCG_C5 value in BLPE default state */

/* MCG_C6: LOLIE0=0,CME0=0,VDIV0=0 */

#define CPU_DEFAULT_BLPE_MCG_C6                            0x00U     /* MCG_C6 value in BLPE default state */

/* MCG_C6: VDIV0|=2 */

#define CPU_DEFAULT_BLPE_MCG_SC                            0x02U     /* MCG_SC value in BLPE default state */

/* OSC_CR: ERCLKEN=0,EREFSTEN=0 */

#define CPU_DEFAULT_BLPE_OSC_CR                            0x00U     /* OSC_CR value in BLPE default state */

/* MCG_C1: CLKS=0,FRDIV|=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

#define CPU_DEFAULT_PEE_MCG_C1                             0x28U     /* MCG_C1 value in PEE default state */

/* MCG_C2: LOCRE0=1,RANGE|=2,EREFS=1 */

#define CPU_DEFAULT_PEE_MCG_C2                             0xA4U     /* MCG_C2 value in PEE default state */

/* MCG_C4: DMX32=0,DRST_DRS=0 */

#define CPU_DEFAULT_PEE_MCG_C4                             0x00U     /* MCG_C4 value in PEE default state */

/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0|=5 */

#define CPU_DEFAULT_PEE_MCG_C5                             0x05U     /* MCG_C5 value in PEE default state */

/* MCG_C6: PLLS=1,CME0=0,VDIV0|=0x18 */

#define CPU_DEFAULT_PEE_MCG_C6                             0x58U     /* MCG_C6 value in PEE default state */

/* MCG_C6: VDIV0|=2 */

#define CPU_DEFAULT_PEE_MCG_SC                             0x02U     /* MCG_SC value in PEE default state */

/* OSC_CR: ERCLKEN=0,EREFSTEN=0 */

#define CPU_DEFAULT_PEE_OSC_CR                             0x00U     /* OSC_CR value in PEE default state */

/* MCG_C1: CLKS|=2,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

#define CPU_DEFAULT_PBE_MCG_C1                             0x80U     /* MCG_C1 value in PBE default state */

/* MCG_C2: LOCRE0=1,RANGE|=2,EREFS=1 */

#define CPU_DEFAULT_PBE_MCG_C2                             0xA4U     /* MCG_C2 value in PBE default state */

/* MCG_C4: DMX32=0,DRST_DRS=0 */

#define CPU_DEFAULT_PBE_MCG_C4                             0x00U     /* MCG_C4 value in PBE default state */

/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0|=5 */

#define CPU_DEFAULT_PBE_MCG_C5                             0x05U     /* MCG_C5 value in PBE default state */

/* MCG_C6: PLLS=1,CME0=0,VDIV0|=0x18 */

#define CPU_DEFAULT_PBE_MCG_C6                             0x58U     /* MCG_C6 value in PBE default state */

/* MCG_C6: VDIV0|=2 */

#define CPU_DEFAULT_PBE_MCG_SC                             0x02U     /* MCG_SC value in PBE default state */

/* OSC_CR: ERCLKEN=0,EREFSTEN=0 */

#define CPU_DEFAULT_PBE_OSC_CR                             0x00U     /* OSC_CR value in PBE default state */

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‎05-04-2015 07:39 AM
298 Views
soledad
NXP Employee
NXP Employee

Hello Aaron,

The BSP for the twrk60 is configured in order to use a 50 MHz XTAL if your board doesn’t have the same characteristics, then you need to modify the BSP.

Attached to this mail, you can find a document that shows how-to Change Default Clock Settings in Kinetis BSPs


Have a great day,
Sol

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