Hi, i have a custom board using 5775E running MII-Lite mode with tja1100 autonomous mode. i was able check that both the transmission (polling every 1 second, sending a dummy udp packet) and reception works once (interrupt driven). then no subsequent packages are sent/received any more. i was also able to talk to tja via the MDIO/MDC interface to read/write register values.
my assumption is that if i can send and receive the packs one time (verified by wireshark) then the wiring, phy, clocks should be cleared.. any suggestion where to look next?
I'm sure i did
// Clear interrupt
FEC.EIR.R = 0x02000000;
at the end of the receive interrupt and nothing special about the sending with
FEC.TDAR.R = 0x01000000; // Start transmission
the initialization code was adapted from a 5748G udp example from the forum. i see only the descriptor/buffer definitions are different from the 5777c example. the alignment of the descriptors and buffers are set to (16).
any comments welcome.. running out of ideas.
thanks for the hint. the way i enabled the caches is in the startup.s first lines with:
#define Z7_0_ICACHE_ENABLE 0
#define Z7_0_DCACHE_ENABLE 0
can you point me to how to "check it in debugger and if it allows see which variables are cached." in Design Studio ?
since i'm able to communicate one time, i would assume the IO setups and interrupt setups ok.. i'm attaching the driver sections i appreciate if you can take a closer look at the data structures that was adapted from
i also borrowed a few apis from the link you mentioned and verified that the TJA1100 is talking correctly via MDIO/MDC.
the status0 changes from 35840 (0x8C00) to 3072 (0xC00) after the first transmission but no change afterward (remains 0x8C00).
status8 in the descriptor do not seem to change (18432 or 0x4800) after writing to TDAR bit to 1.
TDAR seems to be 0 all the time by stepping through
it really seems the data cache is enabled, but you wrote you disabled it. Anyway you can check it in debugger and if it allows see which variables are cached.
Are status bits in descriptors changed after transmission and reception and what about the RDAR/TDAR?
For the init be sure descriptors and buffers are properly aligned and descriptor rings is set (last descriptor has wrap bit set.
You can refer to below code for basic init
hmm.. dug a bit more.. it seems the 5748G has an "enhanced buffer descriptor feature" that is not available on the 5777C.. the descriptor format i used was from the 5748G with the "enhanced feature" 1588 enabled so it does not match the one on the 5777C..
i changed the descriptor format from the enhanced to legacy now it behaves normal. i'm able to see the consecutive packets sent and received..
i would like to then ask the follow up question regarding how to disable or enable the caching on this particular piece of ram? for performance reason, it is still desirable to enable the cache. any pragma ?
use an MMU, for a setting you can refer to MMU Assist Register CONFIGURATOR
Ideally create a custom linker section in the linker file (.ld), where decriptors and buffers will be placed into and cover it by TLB entry in MMU with cache inhibit bit set.