eTPU2 triggered DMA to eQADC

[AndreiC]

I'm working with the MPC5634M, but I expect that many processors have similar peripherals. I'm using gcc in S32DS.

My quest is to have engine synchronized ADC readings, rather than uniform timer triggers or random software initiated conversions. I'd love to have DMA delivery of a set of readings that I'll post-process when I get the DMA interrupt, maybe even decimated results. I could have an interrupt and have to go unload the results FIFO. I'll settle for something that smelled like it works. As it is, I've spent two weeks on this section and I can't get the ADC to trigger.

I'm using the CRANK and CAM eTPU2 functions to synchronize with a Diesel engine, and this portion works very well. I'm using FUEL and KNOCK on 26 channels and it's very reliable.

I have the ADC working with software initiated conversions but, of course, the ADC conversion timing is all over the place and not synchronized with the engine.

In the documentation are a few references to using the eTPU to act as a trigger to have the DMA unit feed conversion commands into the FIFOs. Going through app notes AN3396 and AN4209 I've managed to set up an ADC command queue (and I can feed these commands into the FIFO and successfully trigger them via software mode), and I've set up the trigger to look at eTPU channel 31 (apparently only the top 6 channels can be used as triggers).

I've set up the DMA unit channel 0 to have a source as my command array, destination as the ADC command queue 0, 32-bits wide, transfer 4 bytes at a time, increment the source, don't increment the destination, just like the sample code in the app notes that use the eMIOS as a trigger.

I've set up the eTPU to use the KNOCK function to generate a set of 16 pulses, and I can see these being generated on the output pin via my oscilloscope. They are precisely where I told them to be.

I've set up the SIU to feed eTPU31 to the ADC trigger:

SIU.ISEL3.B.ETSEL0 = 0x0F; /* 15.8.20 select eTPU channel 31 in the mux */

SIU.ETISR.B.TSEL0 = 0x00; /* Use the mux as the conversion trigger */  /* Section 15.8.17 in RM */

I start the ADC to use the "Rising Edge External Trigger, Single Scan" trigger mode.

I can look through the ADC device registers and see that the ADC is waiting for a trigger. I can see the eTPU generating the trigger by the trace on my 'scope. I can see the bits set in the SIU to feed the eTPU into the ADC trigger.

But will it trigger? NOOOOOOO!

I'm in the process of writing a minimal test program that shows the problem, but this includes eTPU, DMA, eQADC, and it takes a while to make small and clear. 

Does anybody have any sample code that shows how to do eTPU triggered ADC conversions? Is there a better way, like using the STAC bus to feed in TCR2? Is there some weird feature that I'm missing?

I'll post a project once I get something running, or an answer if I stumble across it.

Thanks in advance,

Andrei (from the Great White North)

[AndreiC]

No, I have a call to the function fs_etpu_set_dma_mask_a that sets eTPU->CDTRER_A.R = 0x80000000. So bit 31 on.

Also, in my knock_config_t struct (see AN4907), I set .irq_dma_options = FS_ETPU_DMA_AT_EVERY_TRIGGER.

The documentation is rather vague as to the connection between the eTPU channels and the eQADC. I inferred that the connection was via DMA requests, but that really didn't map into what I was seeing with the eMIOS->DMA->eQADC app note. I tried it both ways, DMA requests on and just assuming that eTPU31 was copied onto the trigger mux.

[davidtosenovjan]

Hi, eTPU DMA request is being triggered by eTPU microcode.

ETPUCDTRSR contains eTPU DMA request statuses. These are set by eTPU DMA request and cleared by the assertion of corresponding DMA completion acknowledge line and these are DMA triggering inputs.

They needs to be enabled in the eTPU Channel n Configuration Register (screenshot below). If you are using GCT tool, then you may see the bit in the screenshot at the very bottom.

Is this the issue?

[AndreiC]

An example of what I am trying to do is on page 2 of AN3772 by David Paterson.

I'm trying to set up that internal data path from the TPU to the ADC (the one that everybody keeps avoiding talking about).

[AndreiC]

In a conversation with another eTPU user, they pointed out table 17 in section 7.1.2 of the MPC563XM RM. This seems to indicate some sort of restriction of DMA to eTPU channels 0,1,2,14,and 15. Other sections indicate that channels 26-31 can be used to trigger DMA.

I'm getting really confused now.