Hi,
I have been running the online bist that i took from the application note AN5288, but when i debug the code it seems that it is stuck in if statement ( if (STCU2->LBESW == 0)), below the status of the register and the code that i have been running:
#include "MPC5777C_on-line_bist_3N45H.h"
#include <stdio.h>
int a=0;
void run_online_bists (void) {
//uint32_t CSM;
//uint32_t SHS;
//uint32_t MB_CSM;
/* ASSUMPTION sysclk: PLL SET TO 50 MHz when this function is called */
SIU->SYSDIV = 0x0000B010;
PLLDIG->PLL0DV =0x2006200F;
/* STCU2 SK Code Register */
/* Unlock write access to the STCU2. */
STCU2->SKC = 0x753F924E; /* Unlock on-line access (key 1) */
STCU2->SKC = 0x8AC06DB1; /* Unlock on-line access (key 2) */
/* STCU2 Configuration Register */
/* STCU2.CFG.B.PTR = 0x10; LBIST 0x00 - 0x5, MBIST 0x10 - 0x50 */
/* STCU2.CFG.B.WRP = 0; Ensure Write Protection for certain STCU2 registers is disabled */
/* STCU2.CFG.B.PMOSEN = 1; Run MBIST Full Test */
/* STCU2.CFG.B.MBU = 0; Run MBIST Full Test */
/* STCU2.CFG.B.CLK_CFG = 1; /* BIST and STCU2 core CLK clock configuration */
/* 000b: sys_clk */
/* 001b: sys_clk/2 */
/* ... */
/* 111b: sys_clk/8 */
STCU2->CFG = 0x10000011;
/* STCU2 Watchdog Register Granularity */
/* Allow maximum time BIST execution time */
STCU2->WDG = 0x000395F8; /* Watchdog End of Count Timer = (value+1) x 16 STCU2 core clock cycles */
/* STCU2 Error FM Register */
STCU2->ERR_FM = 0; /* Map all STCU2 faults as recoverable */
/* STCU2 On-Line LBIST Reset Management */
STCU2->LBRMSW = 0x0000003F; /* Generate global reset after last LBIST */
/* STCU2 LBIST Unrecoverable FM Register */
STCU2->LBUFM = 0; /* Map all LBISTs faults as recoverable */
/* STCU2 MBIST Unrecoverable FM Registers */
STCU2->MBUFML = 0; /* Map all low numbered MIBSTs faults as recoverable */
STCU2->MBUFMM = 0; /* Map all mid numbered MIBSTs faults as recoverable */
STCU2->MBUFMH = 0; /* Map all high numbered MIBSTs faults as recoverable */
STCU2->SKC = 0x8AC06DB1; /* Key2-extend STCU2 reg access to prevent Hard-coded WDG timeout */
/* STCU2 MBIST Control Registers */
STCU2->MB_CTRL[0] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 0: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[0] = STCU2_MB_CTRL_PTR(0x11)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 0: Pointer to MBIST1 */
STCU2->MB_CTRL[1] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 1: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[1] = STCU2_MB_CTRL_PTR(0x12)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 1: Pointer to MBIST2 */
STCU2->MB_CTRL[2] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 2: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[2] = STCU2_MB_CTRL_PTR(0x13)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 2: Pointer to MBIST3 */
STCU2->MB_CTRL[3] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 3: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[3] = STCU2_MB_CTRL_PTR(0x14)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 3: Pointer to MBIST4 */
STCU2->MB_CTRL[4] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 4: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[4] = STCU2_MB_CTRL_PTR(0x15)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 4: Pointer to MBIST5 */
STCU2->MB_CTRL[5] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 5: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[5] = STCU2_MB_CTRL_PTR(0x16)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 5: Pointer to MBIST6 */
STCU2->MB_CTRL[6] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 6: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[6] = STCU2_MB_CTRL_PTR(0x17)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 6: Pointer to MBIST7 */
STCU2->MB_CTRL[7] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 7: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[7] = STCU2_MB_CTRL_PTR(0x18)| STCU2_LB_CTRL_CSM_MASK;; /* MBIST 7: Pointer to MBIST8 */
STCU2->MB_CTRL[8] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 8: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[8] = STCU2_MB_CTRL_PTR(0x19)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 8: Pointer to MBIST9 */
STCU2->MB_CTRL[9] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 9: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[9] = STCU2_MB_CTRL_PTR(0x1A)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 9: Pointer to MBIST10 */
STCU2->MB_CTRL[10] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 10: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[10] = STCU2_MB_CTRL_PTR(0x1B)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 10: Pointer to MBIST11 */
STCU2->MB_CTRL[11] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 11: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[11] = STCU2_MB_CTRL_PTR(0x1C)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 11: Pointer to MBIST12 */
STCU2->MB_CTRL[12] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 12: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[12] = STCU2_MB_CTRL_PTR(0x1D)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 12: Pointer to MBIST13 */
STCU2->MB_CTRL[13] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 13: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[13] = STCU2_MB_CTRL_PTR(0x1E)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 13: Pointer to MBIST14 */
STCU2->MB_CTRL[14] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 14: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[14] = STCU2_MB_CTRL_PTR(0x1F)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 14: Pointer to MBIST15 */
STCU2->MB_CTRL[15] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 15: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[15] = STCU2_MB_CTRL_PTR(0x20)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 15: Pointer to MBIST16 */
STCU2->MB_CTRL[16] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 16: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[16] = STCU2_MB_CTRL_PTR(0x21)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 16: Pointer to MBIST17 */
STCU2->MB_CTRL[17] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 17: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[17] = STCU2_MB_CTRL_PTR(0x22)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 17: Pointer to MBIST18 */
STCU2->MB_CTRL[18] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 18: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[18] = STCU2_MB_CTRL_PTR(0x23)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 18: Pointer to MBIST19 */
STCU2->MB_CTRL[19] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 19: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[19] = STCU2_MB_CTRL_PTR(0x24)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 19: Pointer to MBIST20 */
STCU2->MB_CTRL[20] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 20: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[20] = STCU2_MB_CTRL_PTR(0x25)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 20: Pointer to MBIST21 */
STCU2->MB_CTRL[21] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 21: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[21] = STCU2_MB_CTRL_PTR(0x26)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 21: Pointer to MBIST22 */
STCU2->SKC = 0x8AC06DB1; /* Key2-extend STCU2 reg access to prevent Hard-coded WDG */
STCU2->MB_CTRL[22] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 22: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[22] = STCU2_MB_CTRL_PTR(0x27)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 22: Pointer to MBIST23 */
STCU2->MB_CTRL[23] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 23: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[23] = STCU2_MB_CTRL_PTR(0x28)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 23: Pointer to MBIST24 */
STCU2->MB_CTRL[24] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 24: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[24] = STCU2_MB_CTRL_PTR(0x29)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 24: Pointer to MBIST25 */
STCU2->MB_CTRL[25] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 25: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[25] = STCU2_MB_CTRL_PTR(0x2A)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 25: Pointer to MBIST26 */
STCU2->MB_CTRL[26] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 26: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[26] = STCU2_MB_CTRL_PTR(0x2B)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 26: Pointer to MBIST27 */
STCU2->MB_CTRL[27] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 27: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[27] = STCU2_MB_CTRL_PTR(0x2C)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 27: Pointer to MBIST28 */
STCU2->MB_CTRL[28] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 28: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[28] = STCU2_MB_CTRL_PTR(0x2D)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 28: Pointer to MBIST29 */
STCU2->MB_CTRL[29] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 29: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[29] = STCU2_MB_CTRL_PTR(0x2E)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 29: Pointer to MBIST30 */
STCU2->MB_CTRL[30] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 30: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[30] = STCU2_MB_CTRL_PTR(0x2F)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 30: Pointer to MBIST31 */
STCU2->MB_CTRL[31] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 31: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[31] = STCU2_MB_CTRL_PTR(0x30)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 31: Pointer to MBIST32 */
STCU2->MB_CTRL[32] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 32: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[32] = STCU2_MB_CTRL_PTR(0x31)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 32: Pointer to MBIST33 */
STCU2->MB_CTRL[33] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 33: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[33] = STCU2_MB_CTRL_PTR(0x32)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 33: Pointer to MBIST34 */
STCU2->MB_CTRL[34] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 34: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[34] = STCU2_MB_CTRL_PTR(0x33)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 34: Pointer to MBIST35 */
STCU2->MB_CTRL[35] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 35: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[35] = STCU2_MB_CTRL_PTR(0x34)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 35: Pointer to MBIST36 */
STCU2->MB_CTRL[36] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 36: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[36] = STCU2_MB_CTRL_PTR(0x35)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 36: Pointer to MBIST37 */
STCU2->MB_CTRL[37] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 37: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[37] = STCU2_MB_CTRL_PTR(0x36)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 37: Pointer to MBIST38 */
STCU2->MB_CTRL[38] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 38: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[38] = STCU2_MB_CTRL_PTR(0x37)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 38: Pointer to MBIST39 */
STCU2->MB_CTRL[39] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 39: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[39] = STCU2_MB_CTRL_PTR(0x38)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 39: Pointer to MBIST40 */
STCU2->MB_CTRL[40] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 40: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[40] = STCU2_MB_CTRL_PTR(0x39)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 40: Pointer to MBIST41 */
STCU2->MB_CTRL[41] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 41: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[41] = STCU2_MB_CTRL_PTR(0x3A)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 41: Pointer to MBIST42 */
STCU2->SKC = 0x8AC06DB1; /* Key2-extend STCU2 reg access to prevent Hard-coded WDG */
STCU2->MB_CTRL[42] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 42: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[42] = STCU2_MB_CTRL_PTR(0x3B)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 42: Pointer to MBIST43 */
STCU2->MB_CTRL[43] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 43: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[43] = STCU2_MB_CTRL_PTR(0x3C)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 43: Pointer to MBIST44 */
STCU2->MB_CTRL[44] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 44: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[44] = STCU2_MB_CTRL_PTR(0x3D)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 44: Pointer to MBIST45 */
STCU2->MB_CTRL[45] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 45: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[45] = STCU2_MB_CTRL_PTR(0x3E)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 45: Pointer to MBIST46 */
STCU2->MB_CTRL[46] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 46: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[46] = STCU2_MB_CTRL_PTR(0x3F)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 46: Pointer to MBIST47 */
STCU2->MB_CTRL[47] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 47: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[47] = STCU2_MB_CTRL_PTR(0x40)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 47: Pointer to MBIST48 */
STCU2->MB_CTRL[48] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 48: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[48] = STCU2_MB_CTRL_PTR(0x41)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 48: Pointer to MBIST49 */
STCU2->MB_CTRL[49] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 49: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[49] = STCU2_MB_CTRL_PTR(0x42)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 49: Pointer to MBIST50 */
STCU2->MB_CTRL[50] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 50: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[50] = STCU2_MB_CTRL_PTR(0x43)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 50: Pointer to MBIST51 */
STCU2->MB_CTRL[51] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 51: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[51] = STCU2_MB_CTRL_PTR(0x44)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 51: Pointer to MBIST52 */
STCU2->MB_CTRL[52] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 52: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[52] = STCU2_MB_CTRL_PTR(0x45)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 52: Pointer to MBIST53 */
STCU2->MB_CTRL[53] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 53: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[53] = STCU2_MB_CTRL_PTR(0x46)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 53: Pointer to MBIST54 */
STCU2->MB_CTRL[54] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 54: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[54] = STCU2_MB_CTRL_PTR(0x47)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 54: Pointer to MBIST55 */
STCU2->MB_CTRL[55] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 55: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[55] = STCU2_MB_CTRL_PTR(0x48)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 55: Pointer to MBIST56 */
STCU2->MB_CTRL[56] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 56: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[56] = STCU2_MB_CTRL_PTR(0x49)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 56: Pointer to MBIST57 */
STCU2->MB_CTRL[57] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 57: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[57] = STCU2_MB_CTRL_PTR(0x4A)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 57: Pointer to MBIST58 */
STCU2->MB_CTRL[58] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 58: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[58] = STCU2_MB_CTRL_PTR(0x4B)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 58: Pointer to MBIST59 */
STCU2->SKC = 0x8AC06DB1; /* Key2-extend STCU2 reg access to prevent Hard-coded WDG */
STCU2->MB_CTRL[59] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 59: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[59] = STCU2_MB_CTRL_PTR(0x4C)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 59: Pointer to MBIST60 */
STCU2->MB_CTRL[60] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 60: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[60] = STCU2_MB_CTRL_PTR(0x4D)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 60: Pointer to MBIST61 */
STCU2->MB_CTRL[61] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 61: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[61] = STCU2_MB_CTRL_PTR(0x4E)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 61: Pointer to MBIST62 */
STCU2->MB_CTRL[62] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 62: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[62] = STCU2_MB_CTRL_PTR(0x4F)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 62: Pointer to MBIST63 */
STCU2->MB_CTRL[63] = STCU2_LB_CTRL_CSM_MASK; /* MBIST 63: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[63] = STCU2_MB_CTRL_PTR(0x50)| STCU2_LB_CTRL_CSM_MASK; /* MBIST 63: Pointer to MBIST64 */
STCU2->MB_CTRL[64] = 0; /* MBIST 64: 0=Sequential, 1 = concurrent mode */
STCU2->MB_CTRL[64] = STCU2_MB_CTRL_PTR(0x01); /* MBIST 64: Pointer to LBIST1 */
/* LBIST Execution Order: 1 2 5 0 4 3 */
/* Program LBIST CTRL, PCS, and MISR Expected High Registers Registers */
/* STCU2->LB[n].LB_CTRL - STCU2 LBISTn Control Register */
/* STCU2->LB[n].LB_PCS - STCU2 LBIST PC Stop Register */
/* STCU2->LB[n].LB_MISREHSW - STCU2 On-Line LBIST MISR Expected High Register */
/* STCU2->LB[n].LB_MISRELSW - STCU2 On-Line LBIST MISR Expected Low Register */
/* LBIST0 */
STCU2->LB[0].CTRL = 0x04004504; /* STCU2_LB_CTRL0: Run Sequentially, next in sequence is LBIST4, SHS = 0 */
STCU2->LB[0].PCS = 0x4C0;
STCU2->LB[0].MISRELSW = 0x638CABD3;
STCU2->LB[0].MISREHSW = 0xF6FEF134;
/* LBIST1 */
STCU2->LB[1].CTRL = 0x02004504; /* STCU2_LB_CTRL1: Run Sequentially, next in sequence is LBIST2, SHS = 0 */
STCU2->LB[1].PCS = 0x340;
STCU2->LB[1].MISRELSW = 0x29CAE1DA;
STCU2->LB[1].MISREHSW = 0xF547396A;
/* LBIST2 */
STCU2->LB[2].CTRL = 0x05004504; /* STCU2_LB_CTRL2: Run Sequentially, next in sequence is LBIST5, SHS = 0 */
STCU2->LB[2].PCS = 0x500;
STCU2->LB[2].MISRELSW = 0x1AC8F17C;
STCU2->LB[2].MISREHSW = 0x84F64979;
/* LBIST3 */
STCU2->LB[3].CTRL = 0x7F004504; /* STCU2_LB_CTRL3: Run Sequentially, last in sequence, SHS = 0 */
STCU2->LB[3].PCS = 0xA00;
STCU2->LB[3].MISRELSW = 0xC59BF565;
STCU2->LB[3].MISREHSW = 0x555F4ACF;
/* LBIST4 */
STCU2->LB[4].CTRL = 0x03004504; /* STCU2_LB_CTRL4: Run Sequentially, next in sequence is LBIST3, SHS = 0 */
STCU2->LB[4].PCS = 0xA40;
STCU2->LB[4].MISRELSW = 0x15C9A73F;
STCU2->LB[4].MISREHSW = 0xBD55BE6A;
/* LBIST5 */
STCU2->LB[5].CTRL = 0x00004504; /* STCU2_LB_CTRL5: Run Sequentially, next in sequence is LBIST0, SHS = 0 */
STCU2->LB[5].PCS = 0x1740;
STCU2->LB[5].MISRELSW = 0x6A3C6D9C;
STCU2->LB[5].MISREHSW = 0x3AB9877C;
/* STCU2 Run Software Register */
STCU2->RUNSW = 0x00000301; /* STCU2_RUNSW: MBIE=0, M/LBSWPLLEN=1, RUNSW=1 */
}
void err_lbist_sw_failed (void) {
while (1){
a=1;
} /* trap */
}
void err_lbist_sw_incomplete (void) {
while (1){
a=2;
} /* trap */
}
void err_mbist_sw_failed (void) {
while (1){
a=3;
} /* trap */
}
void err_mbist_sw_incomplete (void) {
while (1){
a=4;
} /* trap */
}
void err_stcu2_error (void) {
while (1){
a=5;
} /* trap */
}
void err_misr_error (void) {
while (1){
a=6;
} /* trap */
}
void read_online_bists_results (void) {
/* Check for failed on-line LBIST */
if (STCU2->LBSSW ==STCU2_LBSSW_LBSSW0_MASK) { /* If on-line LBIST0 failure */
err_lbist_sw_failed(); /* Go to LBIST on-line failed routine */
}
/* Verify on-line LBIST execution ended */
if (STCU2->LBESW == 0) { /* If on-line LBIST0 did not complete */
err_lbist_sw_incomplete(); /* Go to LBIST on-line incomplete routine */
}
/* Check for failed on-line MBIST */
if (STCU2->MBSLSW ==STCU2_MBSLSW_MBSSW0_MASK) { /* If on-line MBIST0 failure */
err_mbist_sw_failed(); /* Go to MBIST on-line failed routine */
}
/* Verify on-line LBIST execution ended */
if (STCU2->MBELSW == 0) { /* If on-line MBIST0 did not complete */
err_mbist_sw_incomplete(); /* Go to MBIST on-line incomplete routine */
}
/* Check for internal STCU2 engine/parameters failure */
if ((STCU2->ERR_STAT == STCU2_ERR_STAT_INVPSW_MASK) || (STCU2->ERR_STAT == STCU2_ERR_STAT_ENGESW_MASK) || (STCU2->ERR_STAT == STCU2_ERR_STAT_WDTOSW_MASK) || (STCU2->ERR_STAT == STCU2_ERR_STAT_LOCKESW_MASK)){
/* If there was one STCU2 on-line error */
err_stcu2_error(); /* Go to STCU2 error routine */
}
}
Main function:
/* Including necessary module. Cpu.h contains other modules needed for compiling.*/
#include "Cpu.h"
#include "pin_mux.h"
#include "MPC5777C_on-line_bist_3N45H.h"
volatile int exit_code = 0;
/* User includes (#include below this line is not maintained by Processor Expert) */
#include <stdint.h>
#include <stdbool.h>
/*!
\brief The main function for the project.
\details The startup initialization sequence is the following:
* - startup asm routine
* - main()
*/
#define PORT PTD
#define LED 21
void delay(volatile int cycles)
{
/* Delay function - do nothing for a number of cycles */
while(cycles--);
}
int main(void)
{
/* Write your local variable definition here */
/*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/
#ifdef PEX_RTOS_INIT
PEX_RTOS_INIT(); /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */
#endif
/*** End of Processor Expert internal initialization. ***/
run_online_bists ();
read_online_bists_results ();
/* Write your code here */
/* For example: for(;;) { } */
/* Initialize LED */
PINS_DRV_Init(NUM_OF_CONFIGURED_PINS, g_pin_mux_InitConfigArr);
while(1)
{
/* Insert a small delay to make the blinking visible */
delay(720000);
/* Toggle output value LED1 */
PINS_DRV_TogglePins(PORT, (1 << LED));
}
/*** Don't write any code pass this line, or it will be deleted during code generation. ***/
/*** RTOS startup code. Macro PEX_RTOS_START is defined by the RTOS component. DON'T MODIFY THIS CODE!!! ***/
#ifdef PEX_RTOS_START
PEX_RTOS_START(); /* Startup of the selected RTOS. Macro is defined by the RTOS component. */
#endif
/*** End of RTOS startup code. ***/
/*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/
for(;;) {
if(exit_code != 0) {
break;
}
}
return exit_code;
/*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/
} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/
/* END main */
/*!
** @}
*/
/*
** ###################################################################
**
** This file was created by Processor Expert 10.1 [05.21]
** for the NXP C55 series of microcontrollers.
**
** ###################################################################
*/
