Why CMU_1 Report FLL Event

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Why CMU_1 Report FLL Event

1,063 次查看
zhouxx
Contributor I

Hi:

      I Use CMU_1 to monit the CHKR_CLK;

      System clok Divider 0 is  1, so  CHKR_CLK is 100MHz;

      I set CMU_1 HFREF 440  LFREF 360, why the CMU_1 report FLL event?

      Help me Plz。

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891 次查看
lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

solution is to enable lockstep core. LOCKSTEP EN in DCF in UTEST is 1 by default, so this is OK. It just need to be enabled also in boot header:

pastedImage_1.png

Then it will work as expected.

Regards,

Lukas

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891 次查看
zhouxx
Contributor I

Hi:

   I Try to solve the issues by write MC_ME_CCTL2 register,it's working fine。why?

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891 次查看
lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

yes, lock step core will increase the current consumption. The lock step core should be enabled via RCHW, enabling via CCTL2 is not expected use case.

Regards,

Lukas

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891 次查看
zhouxx
Contributor I

tks for your reply。

According what you said,I solved the issues. Enable the lockstep core will increase the system load?

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zhouxx
Contributor I

MPC5746R

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zhouxx
Contributor I

Because CHKR_CLK Is not Enable? How to Eanle the CHKR_CLK

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