Swap feature issue with emulated eeprom driver for MPC5748C

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Swap feature issue with emulated eeprom driver for MPC5748C

680 Views
jiungchoi
Contributor I

Dear professionals.

Swap feature issue with emulated eeprom driver.

mpc5xxx freescale EEPROM Emulation driver is applied in MPC5748C.
I tested with the demo code in the driver, but there was a problem.
When data is written until the active block is full, the first swap is normally performed.
However, when the same operation is performed, the second swap is not performed normally and an error occurs.
At this time, the eepromConf status is as follows:

eepromConf.numberOfBlock = 1
eepromConf.numberOfDeadBlock = 3
eepromConf.activeBlockIndex = 0
eepromConf.blockWriteFlag = 0

I modified the code to match the MPC5748C as follows.

Please answer the experts.

1. user_cfg.h

#ifndef _USER_CFG_H_
#define _USER_CFG_H_
#include "ee_emulation.h"
#include "ee_blocks.h"

#define SCHEME_SELECT ECC32_FIXLENGTH

#define MAX_REERASE 1

#define MAX_REPGM_BLK_IND 1

#define SWAP_CACHE_SIZE 0x30

#define EER_OPTION EER_MCR

#define FLASH_MODULE C55

/* Size of eeprom cache byte*/
#define EE_CACHE_SIZE 0x80

/* Number of eeprom blocks*/
#define NUMBER_OF_BLOCK 4

/* Maximum number of active blocks */
#define NUMBER_OF_ACTIVE_BLOCKS 1

/* Size of buffer */
#define BUFFER_SIZE 0x50

/* Size of data if a fixed length record scheme is selected */
#define DATA_SIZE 0x40

2. Ee_block.h

#define FLASH_REG_BASE 0xFFFE0000
#define LOCK0_REG_OFFSET 0x00000010
#define LOCK1_REG_OFFSET 0x00000014

#define MAIN_ARRAY_BASE 0x00FC0000 /* Base address for EE blocks */

/* Low address space partition 0 :0x00FC0000--0x00FC7FFF*/
#define BLOCK0_OFFSET 0x00000000 /* Offset of low block 0 */
#define BLOCK0_SIZE 0x8000 /* 32KB size */
#define BLOCK0_MASK 0x00000004
#define BLOCK0_PARTITION (0x1<<0)
#define BLOCK0_ADD_SPACE LOW_ADDRESS_SPACE

/* Low address space partition 0 :0x00FC8000--0x00FCFFFF*/
#define BLOCK1_OFFSET 0x00008000 /* Offset of low block 0 */
#define BLOCK1_SIZE 0x8000 /* 32KB size */
#define BLOCK1_MASK 0x00000008
#define BLOCK1_PARTITION (0x1<<0)
#define BLOCK1_ADD_SPACE LOW_ADDRESS_SPACE

/* Mid address space partition 1 :0x00FD0000--0x00FD7FFF*/
#define BLOCK2_OFFSET 0x00010000 /* Offset of low block 1 */
#define BLOCK2_SIZE 0x8000 /* 32KB size */
#define BLOCK2_MASK 0x00000010
#define BLOCK2_PARTITION (0x1<<1)
#define BLOCK2_ADD_SPACE LOW_ADDRESS_SPACE

/* Mid address space partition 1 :0x00FD8000--0x00FDFFFF*/
#define BLOCK3_OFFSET 0x00018000 /* Offset of low block 1 */
#define BLOCK3_SIZE 0x8000 /* 32KB size */
#define BLOCK3_MASK 0x00000020
#define BLOCK3_PARTITION (0x1<<1)
#define BLOCK3_ADD_SPACE LOW_ADDRESS_SPACE

#define UNLOCK_EBLOCKS CLEAR32(FLASH_REG_BASE + LOCK0_REG_OFFSET, 0x03FF03FF)

/* Block address bases */
#define BASE_ADDR_aL_a16K 0xFFFFFFFF
#define BASE_ADDR_aL_a32K 0x00FC0000
#define BASE_ADDR_aL_a64K 0x00FE0000
#define BASE_ADDR_aM_a16K 0x00F90000
#define BASE_ADDR_aM_a32K 0x00FB0000
#define BASE_ADDR_aM_a64K 0xFFFFFFFF
#define BASE_ADDR_aH_a16K 0x00F80000
#define BASE_ADDR_aH_a32K 0xFFFFFFFF
#define BASE_ADDR_aH_a64K 0xFFFFFFFF

2 Replies

568 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

my first question is - have you tried to disable data cache? This is the most common reason for similar troubles. If it is the root cause and if you want to keep data cache enabled, set corresponding flash blocks as cache inhibited. SMPU module can be used for this purpose. Some examples for SMPU configuration can be found here:

Example MPC5748G SMPU initialization GHS614 

https://community.nxp.com/docs/DOC-332545 

There's CI bit (Cache Inhibit) in Word 3 of the descriptor.

Regards,

Lukas

568 Views
jiungchoi
Contributor I

Lucas, Thank you very much for your advice.

Fortunately, I was working with SMPU as well, so it was easy to work with and the issue was resolved.

Regards,

Jiung Choi

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