Some questions about the cache in MPC5674.

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Some questions about the cache in MPC5674.

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lukekim
Contributor II

I have three questions related to the cache of MPC5674.
The followings are the details of my questions.
1. 11.2 16 KB cache organization (P584 ~ P585 in e200z759CRM.pdf)
- What are the correct length of TAG, Lock bits, Dirty bits and Valid bit of cache line format ?
  : TAG - Physical Address Tag (22bit) + Parity (?)
    Lock bits(?)
    Dirty bits (?)
    Valid bit (?)

2. 11.3 Cache lookup (P585 ~ P587 in e200z759CRM.pdf)
- What are the length of the TAG REFERENCE and the OFFSET ?
  My understanding is that the length of TAG is 20. (32bit Address = 20 bits for tag + 7 bits for set(line) + 5 bits for word offset)
  But, in the document, the length of TAG is 22. It's duplicated A[20,21] of physical address and virtual address. Is it correct?
  Almost of documents for cache describes that address size is equal to the sum of tag, index(set) and offset.

3. 11.7.3 Cache line replacement (P597 in e200z759CRM.pdf)
- Please describe the pseduo-round-robin replacement in more detail.
  In the document, the pseduo-round-robin replacement is described as following.
  : There is a single replacement counter for each cache. The replacement algorithm acts as follows:
    On a miss, if the replacement pointer is pointing to a way that is not enabled for replacement (the selected line or way is locked),
    it is incremented until an available way is selected (if any).
    After a cache line is successfully filled without error, the replacement pointer increments to point to the next cache way.
    If no way is available for the replacement, the access is treated as a single beat access and no cache linefill occurs.

  ==> The replacement pointer is pointing to a way. Is the meaning that the replacement pointer is pointing to the first line of a way?
      Actually, we should find a available line to be filled. But, I can't find the description to search an available line in the document.
      Could you check my understanding is correct ?
      a. The replacement point can just point ways.(0 way, 1 way, 2way and 3way)
      b. The replacement point shout move to next way if the way is locked or all of lines in the way are locked.
      3. To find an available line, search sequentially from the first line.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

1) It should be like this:

pastedImage_1.png

2) It'll be rather 2 bits of parity.

pastedImage_2.png

3) No, it just points to the way. Index to cache set (line number) is determined by several bits of virtual address => every address has only one possible set to be stored, but it can be in 4 possible ways.

 

See the picture in the middle of this article, it just shows cache to target memory mapping:

http://alasir.com/articles/cache_principles/cache_line_tag_index.html

 

Hope it helps

310件の閲覧回数
lukekim
Contributor II

Hello David,

Thanks for your rapid response.

Even though your response is very helpful to me, I can't correctly

understand yet.

The followings are additional questions.

1) It should be like this:

https://community.nxp.com/servlet/JiveServlet/downloadImage/

2-946843-194949/pastedImage_1.png

==> It's OK if valid bit and lock bit are 1 bit.

But, I'm still confused because of the below article that is in e200z760RM

document of NXP.

============================================================

=================================================================

9.8.5 EDC Checkbit/Syndrome Coding Scheme Generation—Icache ( at

e200z760RM.pdf)

...

Each tag entry utilizes six check bits to cover the tag + valid bit, and

each double word of data in the data arrays utilizes eight check bits.

...

The lock bits utilize bit-level redundancy, thus are independently

protected.

...

============================================================

=================================================================

Where can I find the six check bits to cover the tag + valid bit ?

Are there no redundant bits for lock?

If lock bit is just 1, how to support EDC/parity check for lock bit?

2) It'll be rather 2 bits of parity.

https://community.nxp.com/servlet/JiveServlet/downloadImage/

2-946843-194950/pastedImage_2.png

<https://community.nxp.com/servlet/JiveServlet/showImage/2-946843-194950/pastedImage_2.png>

==> I think it's related to the answer of the first question.

3) No, it just points to the way. Index to cache set (line number) is

determined by several bits of virtual address => every address has only one

possible set to be stored, but it can be in 4 possible ways.

See the picture in the middle of this article, it just shows cache to

target memory mapping:

http://alasir.com/articles/cache_principles/cache_line_tag_index.html

==> A set has 4 ways.

If all of ways in a set are locked, how to find a way to fill?

Can the replacement pointer point to a way of the next set?

Thanks.

2017-09-26 21:20 GMT+09:00 davidtosenovjan <admin@community.nxp.com>:

NXP Community

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Re: Some questions about the cache in MPC5674.

reply from David Tosenovjan

<https://community.nxp.com/people/davidtosenovjan?et=watches.email.thread>

in MPC5xxx - View the full discussion

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