S32R372 Flash Erase power drop issue

[crow_cy_liao]

Hi All,

When I erase my application software in the FLASH and power drop happened, the boot-loader cannot be turn on anymore.

When I use PEmicro to dump the content of application software in the FLASH, it all shows "XX". I download symbol and do debug step by step, my bootloader is alive but when runs into vpnMpuInit(), which is SDK function and the code is shown as below.

I don't think the bootloader has problem because in general it operates well. It seems to me that the error exists in system so the boot-loader cannot run as usual. Is there any idea which register I should check and then I can do some recovery actions.

void vfnMpuInit(void)
{
/*
* C0(r) | C0(w) | C1(r) | C1(w) | eDMA(r) | eDMA(w) | FRay(r) | FRay(w)
* (M0) (M0)
*
* ZWire | ZWire | ENet | ENet | SPTp(r) | SPTp(w) | C2(r) | C2 (w)
* (M4) (M4)
*
* C0n(r)| C0n(w)| C1n(r)| C1n(w)| SPTs(r) | SPTs(w) | --- | ---
* (M8) (M8)
*
* CSE(r)| CSE(w)|SPTc(r)|SPTc(w)| SPTa(r) | SPTa(w) | C2n(r) | C2n(w
* (M12) (M12)
*
*
*/
/* SMPU_1 is for flash protection */
SMPU_1.RGD[0].WORD0.R = 0x00400000; //protect the UTEST flash
SMPU_1.RGD[0].WORD1.R = 0x00403FFF; //UTEST end address
SMPU_1.RGD[0].WORD2.R = 0x20003003; //only z7-0 core can read UTEST flash
SMPU_1.RGD[0].WORD3.R = 0x00000001; //SMPU_1 descriptor 0 enabled, cache enable

SMPU_1.RGD[1].WORD0.R = 0x00800000; //protect the Emulated EEPROM, start address
SMPU_1.RGD[1].WORD1.R = 0x00807FFF; //block-0/2 EEPROM end address
SMPU_1.RGD[1].WORD2.R = 0x380A38AB; //z7-0 core can read/write, other masters can read;
SMPU_1.RGD[1].WORD3.R = 0x00000003; //cache disable, because this data might be changed in runtime

SMPU_1.RGD[2].WORD0.R = 0x00A00000; //protect the CSE flash
SMPU_1.RGD[2].WORD1.R = 0x00A07FFF; //32K CSE flash end address
SMPU_1.RGD[2].WORD2.R = 0x000030C3; //Only CSE can read/write CSE flash
SMPU_1.RGD[2].WORD3.R = 0x00000001; //protection enable

SMPU_1.RGD[3].WORD0.R = 0x00F98000; //Flash block 0, 16K, bootID for bootloader
SMPU_1.RGD[3].WORD1.R = 0x00F9BFFF; //
SMPU_1.RGD[3].WORD2.R = 0x3C0030C0; //can be read by z4 core, z7 cores
SMPU_1.RGD[3].WORD3.R = 0x00000001; //protection enable

SMPU_1.RGD[4].WORD0.R = 0x00F9C000; //Flash block 1, 16K, bootID for application
SMPU_1.RGD[4].WORD1.R = 0x00F9FFFF; //
SMPU_1.RGD[4].WORD2.R = 0x380A38AB; //can be read by all masters
SMPU_1.RGD[4].WORD3.R = 0x00000003; //protection enable, cache enable

SMPU_1.RGD[5].WORD0.R = 0x00FA0000; //Flash block 2/3/4, 3x64K, code for bootloader
SMPU_1.RGD[5].WORD1.R = 0x00FCFFFF; //
SMPU_1.RGD[5].WORD2.R = 0x3C0F3CFF; //can be read by z4 core, z7 cores
SMPU_1.RGD[5].WORD3.R = 0x00000001; //protection enable, cache enable

SMPU_1.RGD[6].WORD0.R = 0x00FD0000; //Flash block others, 3x64K+6x256K, code for application
SMPU_1.RGD[6].WORD1.R = 0x010FFFFF; //
SMPU_1.RGD[6].WORD2.R = 0x380A38AB; //can be read by all masters
SMPU_1.RGD[6].WORD3.R = 0x00000001; //protection enable, cache enable

/* SMPU_0 is for SRAM, TCM, and peripherals registers protection */
SMPU_0.RGD[0].WORD0.R = 0x40000000; //SRAM protection
SMPU_0.RGD[0].WORD1.R = 0x400FFFFF; //
SMPU_0.RGD[0].WORD2.R = 0x3C0F3CFF; //
SMPU_0.RGD[0].WORD3.R = 0x00000003; //enable protection, disable CPU cache on this area
//for any SRAM area are that shared among multiple cores, it should be set Cache Inhibit
//for any SRAM are that might be modified by DMA or other masters, it should be Cache Inhibit

SMPU_0.RGD[1].WORD0.R = 0x50810000; //core 1 local data RAM
SMPU_0.RGD[1].WORD1.R = 0x5081FFFF;
SMPU_0.RGD[1].WORD2.R = 0x3C0F3CFF; //
SMPU_0.RGD[1].WORD3.R = 0x00000001;

SMPU_0.RGD[2].WORD0.R = 0x50820000; //core 2 local data RAM
SMPU_0.RGD[2].WORD1.R = 0x5082FFFF;
SMPU_0.RGD[2].WORD2.R = 0x3C0F3CFF; //
SMPU_0.RGD[2].WORD3.R = 0x00000001;

SMPU_0.RGD[3].WORD0.R = 0xF0000000; //peripheral registers
SMPU_0.RGD[3].WORD1.R = 0xFFFFFFFF; //
SMPU_0.RGD[3].WORD2.R = 0x30033003; //core 1/2 are allowed to read/write any peripherals registers
SMPU_0.RGD[3].WORD3.R = 0x00000003; //cache disabled in this area

SMPU_0.CESR0.B.GVLD = 1; //global enable SMPU_0
SMPU_1.CESR0.B.GVLD = 1; //global enable SMPU_0
}

[lukaszadrapa]

Hi,

if erase operation is terminated by unexpected reset or power-down, the flash is left in undetermined state. This leads to double bit ECC errors. If corrupted flash is accessed (data access or instruction fetch), exception IVOR1 is always triggered (it's not maskable). So, the IVOR1 must be handled appropriately. The only way to recover is to erase affected block(s) again.

Debuggers shows 'XX' or '??' in memory window if the access is terminated by bus error.

We have this application note for MPC56xx devices which could help to understand it:

https://www.nxp.com/docs/en/application-note/AN5200.pdf 

https://www.nxp.com/docs/en/application-note-software/AN5200SW.zip 

Regards,

Lukas