MPC5777C EBI external memory access issue

[prathapvc]

In the following code you will find the EBI Configuration in my application for MPC5777C and D_CS0 is configured to access external SRAM memory and D_CS1 is configured to access external RTRAM memory

void ExternalMemConfiguration()
{
vuint32_t count = 0;

/* Change EBI Physical Base Address to 0x2000_0000 */
External_SRAM_MMU_init();

//SIU.ECCR.R = 0x00001000;
// SIU.ECCR.R = 0x00000181;

/* CS0 PCR 256 */
SIU.PCR[256].R = 0x044C;
/* CS1 PCR 301 */
SIU.PCR[301].R = 0x044C;
/* CS2 PCR 257 */
SIU.PCR[257].R = 0x044C;
/* CS3 PCR 258 */
SIU.PCR[258].R = 0x044C;

/* D_RD_WR PCR 294 */
SIU.PCR[294].R = 0x044C;

/* D_WE0 - D_WE1 PCR 295-296 */
SIU.PCR[295].R = 0x044C;
SIU.PCR[296].R = 0x044C;

/* D_OE PCR 297 */
SIU.PCR[297].R = 0x044C;

/* D_TS PCR 298 */
SIU.PCR[298].R = 0x044C;

/* D_ALE PCR 299 */
SIU.PCR[299].R = 0x044C;

/* D_TA PCR 300 */
SIU.PCR[300].R = 0x044C;

/* D_BDIP PCR 302 */
SIU.PCR[302].R = 0x044C;

/* D_WE2 - D_WE3 PCR 303 - 304 */
SIU.PCR[303].R = 0x044C;
//SIU.PCR[304].R = 0x044C;

/* D_ADD9 - D_ADD11 PCR 305 - 307 */
for (count = 305; count <= 307; count++)
{
SIU.PCR[count].R = 0x044C;
};

/* D_ADD12 - D_ADD15 PCR 259 - 262 */
for (count = 259; count <= 262; count++)
{
SIU.PCR[count].R = 0x044C;
};
/* D_ADD16 - D_ADD30 PCR 263 - 277 */
for (count = 263; count <= 277; count++)
{
SIU.PCR[count].R = 0x044C;
};

/* D_DAT0 - D_DAT15 PCR 278 - 293 */
for (count = 278; count <= 293; count++)
{
SIU.PCR[count].R = 0x044C;
};

//EBI.BMCR.B.BME = 0x0; //Bus Monitor Disabled

/*Base Address: 0x20000803, 16-bit, NoN Mux'd bus */
EBI.CAL[0].BR.R = 0x20001921; //LWRN =1, PS=1,BI=1,V=1,SBL=0,WEBS=1
/* Address Mask: 16MB, Zero Wait States - Flow-Through Sync SRAM */
EBI.CAL[0].OR.R = 0xFF000000;

/* Base Address: 0x20400803, 16-bit, NoN Mux'd bus */
EBI.CAL[1].BR.R = 0x21000807;
/* Address Mask: 16MB, 2 Wait States - */
EBI.CAL[1].OR.R = 0xFF0000F0;

/* Base Address: 0x20800803, 16-bit, NoN Mux'd bus */
EBI.CAL[2].BR.R = 0x22001807;//0x20410803
/* Address Mask: 16MB, 2 Wait States - */
EBI.CAL[2].OR.R = 0xFF0000F0; //8 wait states*/

/* /* Base Address: 0x20C00803, 16-bit, NoN Mux'd bus */
EBI.CAL[3].BR.R = 0x23001801;
/* Address Mask: 16MB, 2 Wait States - */
EBI.CAL[3].OR.R = 0xFE0000F0;

/* MCR - 16-bit mode */
EBI.MCR.R = 0x00000001;

}

void External_SRAM_MMU_init(void)
{
//asm("nofralloc");

asm("lis r3, 0x1002"); /* Select TLB entry #, define R/W replacment control */
asm("mtMAS0 r3"); /* Load MAS0 with 0x1002 0000 for TLB entry #2 */

asm("tlbre"); /* Get TLB entry # information */

asm("mfspr r3, MAS3");
asm("oris r3, r3, 0x2000"); /* EBI Physical Base Addr changed to 0x2000_0000 */
asm("ori r3, r3, 0x0000");

asm("mtMAS3 r3");

asm("msync"); /* make sure we finished all memory accesses */

asm("tlbwe"); /* Write entry defined in MAS0 (entry 1 here) to MMU TLB */

asm("isync"); /* Wait for tlbwe to complete, then flush instruction buffer */
asm("blr");
}

external SRAM memory is accessed through address location - 0x206C2000

external RTRAM memory is accessed through address location - 0x21004000

After accessing (i.e. write operation) external SRAM memory location if external RTRAM memory is accessed (i.e. write operation) it is observed that expected data is not found in the above RTRAM memory address location, please clarify how MPC5777C controller will differentiate these memory locations for different devices as only address lines D_ADD09-D_ADD30 is connected to memory devices

[ashok_majeegb]

Hi David ,

For 16 bit EBI programming can i use attached ,main.c is it alright ? I not seed  any conclusion in this threat . please suggest . 

[Roy741]

Ordinarily alludes to capacity in an outer hard drive or on the Internet. The fundamental "memory" in the PC is the PC's workspace, not its storage space. See outer capacity.

[Ketlon1]

Typically refers to storage in an external hard drive or on the Internet. The main "memory" in the computer is the computer's workspace, not its storage facility. See external storage.

[davidtosenovjan]

Could you please specify used RTRAM device? This acronym says nothing to me..

[prathapvc]

RTRAM is the RAM within the BU-64843 (Data device corporation) device which is basically a MIL-STD-1553 data bus chip. We have configured EBI to access this RTRAM through D_CS1. Please find the attached snapshot of this device connected to MPC5777C

[davidtosenovjan]

Try to use following MMU configuration I have been using in the example

MPC5777C-External SRAM_test-v0_3-GHS714

/*******************************************************************************
Function Name : External_SRAM_MMU_init
Engineer : David Tosenovjan
Date : Feb-07-2020
Parameters :
Modifies :
Returns :
Notes : cache inhibited, 512MBytes (the whole EBI space)
Issues :
*******************************************************************************/
static asm void External_SRAM_MMU_init(void)
{

e_lis r3,0x1002 // Select TLB entry#, define R/W replacment control
mtspr MAS0,r3 // Load MAS0 with 0x1002_0000 for TLB entry #2

e_lis r3,0xc000 // setup 512MBytes to cover the whole EBI space
e_or2i r3,0x0980 // TLB valid, protected from invalidation
mtspr MAS1,r3 // Load MAS1 with 0xC000_0980 for TLB entry #2

se_bgeni r3,2 // virtual address at 0x2000_0000
e_ori r3,r3,0x0038 // VLE, cache-inhibited, write through
mtspr MAS2,r3 // Load MAS2 with 0x2000_0038 for TLB entry #2

se_bgeni r3,2 // physical address at 0x2000_0000
e_ori r3,r3,0x003f // all accesses permitted
mtspr MAS3,r3

msync // make sure we finished all memory accesses
tlbwe // Write entry defined in MAS0 (entry #2 here) to MMU TLB
se_isync // Wait for tlbwe to complete, then flush instruction buffer
}

[prathapvc]

Hi David,

We have configured EBI to access external memory devices in our application as below

a)  External SRAM - CS0 - 0x20000000 - 0x20FFFFFF

b)  RTRAM - CS1 - 0x21000000 - 0x21FFFFFF

c)  DPRAM - CS2 - 0x22000000 - 0x21FFFFFF

d)  DPRAM semaphore - CS3 - 0x23000000 - 0x21FFFFFF

Can you explain the MMU configuration code shared by you and why is it required

[davidtosenovjan]

Because by default BAM configuration MMU TLB entry for EBI space is configured for 16MB i.e. address range 0x2000_0000 - 0x20FF_FFFF.

The code snippet re-configures it for 512MB that is the whole area 0x2000_0000-0x3FFFFFFF.

I don't say it is the reason - just an idea

[prathapvc]

Can there be any EBI bus contention issue since same address lines and data lines are connected to many memory devices

[prathapvc]

Hi David,

After using the MMU configuration you have suggested the issue is not yet resolved. I have attached the source code file below.   

As explained earlier after accessing the address locations ("0x20000002", "0x20000004","0x20000006","0x20000008") if I write data and read back the address location "0x21004000", i am not getting the same data that i had written into this address location. 

In other case, if i dont access the address locations ("0x20000002", "0x20000004","0x20000006","0x20000008") and if I write data and read back the address location "0x21004000", i am getting the same data that i had written earlier into this address location. 

[martinklonfar]

Hi prathapvc,

I am having exactly the same issue with the EBI on MPC5777C. Did You find solution after all? I would really appreciate any hint. Thanks!

  Martin