MPC5777C : EBI Access by Core 0 and Core 1

[Nagendra_Kumar]

Hi,

My application needs external bus accesses for two cores available in 5777C.

I tried disabling cache memories and setting W bit by using this piece of code and pasted in startup file of core 0 and Core 1.

I am using 2nd Entry for TLB in Core 0 and third entry in TLB for Core 1

Core 0 Startup.s

e_lis r3, 0x1002
mtspr 624, r3

e_lis r4, 0xC000
e_or2i r4, 0x0980
mtspr 625, r4

e_lis r5, 0x2000
e_or2i r5, 0x003C
mtspr 626, r5

e_lis r6, 0x2000
e_or2i r6, 0x003f
mtspr 627, r6

tlbwe

Core 1 Startup.s

e_lis r3, 0x1003
mtspr 624, r3

e_lis r4, 0xC000
e_or2i r4, 0x0980
mtspr 625, r4

e_lis r5, 0x2000
e_or2i r5, 0x003C
mtspr 626, r5

e_lis r6, 0x2000
e_or2i r6, 0x003f
mtspr 627, r6

tlbwe

I have configured the Crossbar Switch and set round robin priority for only Slave1: EBI(Do i need to do that for all the slaves?)

I have configured PCU by enable write monitor enable for all the masters for slave 1(EBI ) by writing PCU_CESR register with 0x0000F001.

But i still face some data being corrupted in DPRAM which is used in Core 0.

I need to achieve this without using semaphores in software.

Kindly help me in this regard.

[davidtosenovjan]

For MMU configuration I could offer following useful tool:
https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/MMU-Assist-Register-CONFIGURATOR/ta-p/1110436

It should be enough to set cache inhibited access rigths for EBI slave for both cores and if you set-up round robin it should be enough for EBI.

What you mean by term DPRAM? This is not used in RM of the device.

PCU setting is related to cache content, if accesses to EBI are cache-inhibited, it should not affect. But cache memories should not contain any EBI data thus it is needed to initialize EBI before first EBI access i.e. during system initialization.

[Nagendra_Kumar]

Hi,

Thanks for your Reply,

Sorry for not being clear about DPRAM.

We are using DPRAM (Dual Port Ram) Connected to the external bus of controller.

We are able to read and write the data to DPRAM normally.

DPRAM is accessed via CS0 and accessed only by core 0.

But sometimes the semaphores of the DPRAM are being acquired unintentionally when both cores are running simultaneously using external bus.

However, if i halt one of the core (core 1), the problem does not occur.

Kindly help me in this regard..

[davidtosenovjan]

Could you show me some schematic of connection?