MPC5777C Checker core

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

MPC5777C Checker core

1,331 次查看
darq
Contributor III

Hello,

Is there any documentation on checker core of MPC5777C? What does it do exactly? What are the results of its operation and when? Reference manual seems very limited in this regard.

Best regards

0 项奖励
回复
3 回复数

1,315 次查看
darq
Contributor III

Thank you for your answers.

One last thing that i would like to have clarified is when are specific faults set in FCCU? I assume only fault 10 (RCCU_0) and fault 11 (RCCU_1) are valid for checker core? When is each of them set because description for both of them is the same: "Safety cores out of sync during lockstep. Fault is cleared by clearing the FCCU channel status, FCCU_NCF_Sn[NCFSm]."

Best regards

0 项奖励
回复

1,319 次查看
petervlna
NXP TechSupport
NXP TechSupport

Hello,

Yes, that is basically it. As a user you have access to safety core outputs via FCCU and RCCU.

Only configuration you can do is to enable/disable LSM and to set reaction on fault.

It is only replicating the main core execution. Once there is a mismatch in comparison it will notify the device.

 

best regards,

Peter

0 项奖励
回复

1,328 次查看
Varshap
Contributor I

The MPC5777C is ASILD MCU, its safety core operates in delayed lockstep mode (LSM) to allow the highest safety level to be reached. The checker core will receive all inputs delayed by two clock cycles. Outputs of the checker core will be compared with outputs of the master core. Any differences will be flagged as an error and processed by the FCCU.

 

check for document  - Safety Manual for MPC5777C

0 项奖励
回复