MPC5748g Ethernet: RF interrupts triggered for empty buffers

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MPC5748g Ethernet: RF interrupts triggered for empty buffers

Contributor III

I previously had problems with interrupts not being generated, see I only get one ENET receive interrupt . That problem has been solved.



I'm running my code on a  MPC574XG-MB Evaluation board


I have a local network where the only traffic is ARP packets sent using the Linux arping utitility program from my computer. For each ARP packet I send, one interrupt is generated.


The problem

For the first NUM_RXBDS arping invocations, the packets are written to bd->data. After that, an interrupt is still triggered for each received ARP packet, but the empty flag of bd->status0 is set and bd->length is zero and bd->data contains old ARP packets. Any suggestions why that is so?


What I've tried

I increased NUM_RXBDS from 2 to 5. As before, the first NUM_RXBDS packets were received and the buffer contained the expected ARP packet. But after that, 4/5 sent ARP packets generated an interrupt where the bd->status0 had the empty flag set.


I tried returning early in the ISR if bd->status0 & RX_BD_S0_E but then the interrupt was just triggered immediately again. The led in my main loop stopped blinking.


Tried acknowledging the interrupt when bd->status0 & RX_BD_S0_E. Then my main loop was executed once again, but I didn't get any more data.


Does anyone have suggestions on why I'm receiving RF interrupts when the DMA buffer is empty?


Attaching my WIP EthernetInterface.cpp file which includes the gpio init, intc init, eNBUF init and

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NXP Employee
NXP Employee


it looks like known issue called Cache memory. Memory, which is used for buffer descriptors and sending and receiving frames should be marked as non-cacheable.

Please see SMPU example which shows, how to set memory as non-cacheable.

Example MPC5748G SMPU initialization



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Contributor III

Hi Martin,

Thank you for your suggestion.

I still get empty buffers after the first NUM_RXBDS buffers have been received.

What I've tried

I disabled the caching of the SRAM addresses, by calling DisableMemoryCaching from the EthernetInterface constructor:

void DisableMemoryCaching()
    // TODO(dannas): An experiment to see if it solves my DMA memory not updated problem
    // NXP says we need to disable caching for SRAM:

    // SRAM used by all cores (768kB)
    SMPU_1.RGD[0].WORD0.R = 0x40000000;         // start address
    SMPU_1.RGD[0].WORD1.R = 0x400bffff;         // end address
    SMPU_1.RGD[0].WORD2.FMT0.R = 0xc3ffff00;     // rw set for masters: M0, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13
    SMPU_1.RGD[0].WORD3.B.CI = 1;               // set cache inhibit
    SMPU_1.RGD[0].WORD5.B.VLD = 1;              // enable descriptor[0]

I inspected the SMPU_1.RGD[0] registers in the debugger and they had the expected values. All the other 15 RGD sets were empty.

I verified that all bd->data variables points to addresses within the SRAM (0x4000_000 - 0x400b_ffff). They do.

Any suggestions on how to proceed with the troubleshooting?

The MPC5 Software example list do not list the any ethernet programs, but I have a demo project enet_rmii_udp that I don't know by now where I've found. That one don't include any setup for SMPU. Do you have example code that uses the ENET DMA and sets up SMPU?

Contributor III
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Contributor III

This is my code and it works.

void smpu_config(void)
        // Disable SMPU1 and reconfigure descriptor 0、1、2
        SMPU_1.CES0.B.GVLD = 0;

        // SRAM region 0
        SMPU_1.RGD[0].WORD0.R = 0x40000000; // start address
        SMPU_1.RGD[0].WORD1.R = 0x400000BF; // end address
        SMPU_1.RGD[0].WORD2.FMT0.R = 0xc3ffff00; // rw set for masters: M0, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13
        SMPU_1.RGD[0].WORD5.B.VLD = 1; // enable descriptor[0]

        // SRAM region 1(rxbd、txbd、rxbuffer、txbuffer)
        SMPU_1.RGD[1].WORD0.R = 0x400000C0; // start address
        SMPU_1.RGD[1].WORD1.R = 0x4000193F; // end address
        SMPU_1.RGD[1].WORD2.FMT0.R = 0xc3ffff00; // rw set for masters: M0, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13
        SMPU_1.RGD[1].WORD3.B.CI = 1; // set cache inhibit
        SMPU_1.RGD[1].WORD5.B.VLD = 1; // enable descriptor[0]

        // SRAM region 2
        SMPU_1.RGD[2].WORD0.R = 0x40001940; // start address
        SMPU_1.RGD[2].WORD1.R = 0x400bffff; // end address
        SMPU_1.RGD[2].WORD2.FMT0.R = 0xc3ffff00; // rw set for masters: M0, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13
        SMPU_1.RGD[2].WORD5.B.VLD = 1; // enable descriptor[0]

        // Enable SMPU1 again
        SMPU_1.CES0.B.GVLD = 1;


Get the start address and end address from the .map file

屏幕截图 2022-01-21 105650.png

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