[MPC5748G]  Reset Event

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[MPC5748G]  Reset Event

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manojgovindan
Contributor II

[MPC5748G] : There is any way to generate following reset events  (fake events for testing) . I could not find CFF register in 5748G UM to generate them by simulating the failure.

 

a) Software destructive reset.

b) FCCU failure to react reset.

c) Functional reset escalation.

d)  Voltage/temperature sensor  out of range destructive reset.

e) Voltage/temperature sensor  functional  reset.

f) External reset event.

g) Self-test completed event.

h)  Software destructive event.

i) FCCU hard /soft reaction request event.

j) JTAG initiated reset event.

 

 

Thanks,

Manoj

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11 Replies

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deepikahk
Contributor III

Hi

For FES register how can i trigger the reset events

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manojgovindan
Contributor II

Thanks Peter

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petervlna
NXP TechSupport
NXP TechSupport

Hi,

a) Software destructive reset.

[Peter] - Use mode transition with 0xF as target mode.

b) FCCU failure to react reset.

[Peter] - 1.Disable the FCCU_NCFS_CFGx registers which contains the configuration of each non-critical fault in terms of fault reaction.

              2.Enable the fault sources in NCF Enable Register (FCCU_NCF_Ex)  to allow a transition from the NORMAL into the FAULT or ALARM state.

c) Functional reset escalation.

[Peter] - 1. Set MC_RGM_FRET = 1.

              2. Use mode transition with 0x0 as target mode. (0000 RESET (triggers a ‘functional’ reset event)

d)  Voltage/temperature sensor  out of range destructive reset.

[Peter] - I think only external event (programmable power source / climate chamber)

e) Voltage/temperature sensor  functional  reset.

[Peter] - I think only external event (programmable power source / climate chamber)

f) External reset event.

[Peter] - External reset event (Debugger/ power source / SBC ...)

g) Self-test completed event.

[Peter] - This reset is generated after completion of BIST.

1. Offline - generated when BIST is enabled after successful completion of BIST during reset phase 3.

2. Online - generated when BIST is configured to triggers reset after completion.

h)  Software destructive event.

[Peter] - Same as a)

i) FCCU hard /soft reaction request event.

[Peter] - genarate on FCCU reset reaction on FCCU latched fault. To generate it configure FCCU and inject a fault.

j) JTAG initiated reset event.

The EXTEST, HIGHZ, and CLAMP instructions cause a JTAG 'functional' reset event to occur, which cause JTAG 'functional' reset.

Peter

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deepikahk
Contributor III

Hi,

I tried setting  FCCU failure to react reset event with the information you have provided ,but its not triggering the reset event

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deepikahk
Contributor III

i'm using MPC5744p 

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petervlna
NXP TechSupport
NXP TechSupport

Hi,

MPC5744P implements same mechanism.

Please see the diagram below to understand how FOSU works.

pastedImage_1.png

Peter

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deepikahk
Contributor III

Hi Peter,

               Thanks for the reply..

I want to set the DES and FES register bits

DES register bits as follows

pastedImage_1.png

I tried setting F_SOFT_DEST bit by setting the target mode=0xF in MC_ME_MCTL register and 

F_EDR bit by setting the MC_RGM_FRET=1 and it worked also but except these bit i'm not able to  

set any of the bits can you please help me with this

FES

pastedImage_2.png

How can i set these bits ,how to trigger the reset events for these..

can set this bits by enabling bits this register 'Functional' Bidirectional Reset Enable Register
(MC_RGM_FBRE)

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petervlna
NXP TechSupport
NXP TechSupport

Hi,

I will try to explain it.

DES register:

F_VOR_DEST - A voltage out of range 'destructive' reset event has occurred

" This event is triggered when voltage detectors detect that voltage is out of spec" Use programmable power supply and set it in way that input voltage will violate defined thresholds. If you remove power completely you will loose also RGM module register content.

F_TSR_DEST - You can trigger it by using temperature chamber by violating specified temperatures for micro.

F_FIF - This reset is internal and cannot be triggered by user for test. Flash initialization is done in reset phase 2.

F_EDR -  'functional' reset escalation - triggered by exceeding of configured number of functional resets.

F_SUF - Triggered by STCU2 itself when BIST find multibit ECC error during its test.

F_SUF - Fault triggered by STCU internally during reset. Cant be externally set.

F_FFRR - Reset triggered by FOSU. Described in this thread. 

F_SOFT_DEST - SW destructive reset triggered by RGM. Can be triggered via SW mode transition.

F_POR - Power on reset flag.

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deepikahk
Contributor III

For POR power on reset is there any fake event so i can trigger it

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petervlna
NXP TechSupport
NXP TechSupport

The only way is to interrupt power supply line.

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deepikahk
Contributor III

Thanks peter

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