MPC5668G DSPI_C only accessible by Core z0; maybe depends on AIPS/AXBS?
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Hello everybody,
at first of all, I'm sorry because of my not very good English!
I'm working on the MPC5668G which has two Cores z0 and z6. I have to use the DSPI module and I can only use the DSPI_C interface. Until now I was using only the z6 Core and while I wanted to implement the code for DSPI_C, I got a DTLB (Data Translation Lookaside Buffer) error on the debugger.
I have tested the other DSPI interfaces (DSPI_A, DSPI_B, DSPI_D) and the other Core z0 and I could determine, that
the Core z6 can successfully access only the DSPI_A and DSPI_B interfaces,
while
the Core z0 can successfully access only the DSPI_C and DSPI_D interfaces.
I have looked up to into the Reference Manual (RM) and I have seen one difference:
DSPI_A and DSPI_B are within the memory region AIPS_B (AXBS Port S7)
while
DSPI_C and DSPI_B are within the memory region AIPS_A (AXBS Port S6)
So, I think, that the AIPS_A is only accessible by Core z0 and the AIPS_B is only accessible by Core z6. But in the RM I can't see this information. So could you please explain me, if I am right or if it is possible to change configurations?
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Hi, not really. It can be accessed by e200z6 core as well but is is needed to define MMU region for AIPS_A space,
We have been using following MMU setting in Lauterbach:
;MMUSCR0: enable address translation bypass
Data.Set SPR:0x3F4 %LONG 0x80000000
;set up TLBs
MMU.TLB1.SET 0. 0xC0000500 0xFFF0002A 0xFFF0003F ;peripherals and boot rom
MMU.TLB1.SET 1. 0xC0000900 0x00000020 0x0000003F ;FLASH
MMU.TLB1.SET 2. 0xC0000900 0x20000020 0x2000003F ;external SRAM
MMU.TLB1.SET 3. 0xC0000500 0x40000028 0x4000003F ;internal SRAM
MMU.TLB1.SET 4. 0xC0000500 0xC3F00008 0xC3F0003F ;AIPS_A
In Codewarrior it is configured in INIT_Derivative function.
AIPS_A must be initialized:
/* Write one MMU Table Entry: */
/* r3, r4, r5 and r6 must hold */
/* the values of MAS0, MAS1, MAS2 and MAS3 */
asm void InitAIPS_A( void )
{
nofralloc
mflr r29 /* Save off return address in NV reg */
// MMU.TLB1.SET 4. 0xC0000500 0xC3F00008 0xC3F0003F ;AIPS_A
#define MAS0_AIPS_A 0x10040000
#define MAS1_AIPS_A 0xC0000500
#define MAS2_AIPS_A 0xC3F00008
#define MAS3_AIPS_A 0xC3F0003F
e_lis r3, MAS0_AIPS_A@h
e_or2i r3, MAS0_AIPS_A@l
e_lis r4, MAS1_AIPS_A@h
e_or2i r4, MAS1_AIPS_A@l
e_lis r5, MAS2_AIPS_A@h
e_or2i r5, MAS2_AIPS_A@l
e_lis r6, MAS3_AIPS_A@h
e_or2i r6, MAS3_AIPS_A@l
msync
se_isync
bl WriteMMUTableEntry
se_isync
mtlr r29
blr
}
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Thanks a lot . Your code is working. For other people, that are using GCC and not CodeWarrior like me, here is my code with GCC-specific syntax for asm code:
__asm __volatile(
//MAS0_AIPS_A Konfiguration: 0x10040000
//MAS1_AIPS_A Konfiguration: 0xC0000500
//MAS2_AIPS_A Konfiguration: 0xC3F00008
//MAS3_AIPS_A Konfiguration: 0xC3F0003F
"mflr %r29; \
e_lis %r3, 0x10040000@h; \
e_or2i %r3, 0x10040000@l; \
e_lis %r4, 0xC0000500@h; \
e_or2i %r4, 0xC0000500@l; \
e_lis %r5, 0xC3F00008@h; \
e_or2i %r5, 0xC3F00008@l; \
e_lis %r6, 0xC3F0003F@h; \
e_or2i %r6, 0xC3F0003F@l; \
msync; \
se_isync;"
/* se_bl WriteMMUTableEntry; \*/
/* Write MMU Assist Register 0 (MAS0); SPR 624 */
"mtspr 624, %r3;"
/* Write MMU Assist Register 1 (MAS1); SPR 625 */
"mtspr 625, %r4;"
/* Write MMU Assist Register 2 (MAS2); SPR 626 */
"mtspr 626, %r5;"
/* Write MMU Assist Register 3 (MAS3); SPR 627 */
"mtspr 627, %r6;"
/* Write the table entry */
"tlbwe;"
"se_isync; \
mtlr %r29;"
);