MPC5643L create SRAM region uncacheable

[Pat]

Hi,

Now, I have a MMU TLB entry definition for the SRAM as : TSIZE of 128K and cacheable.

I would like create a new region of i.e 2KB of SRAM uncacheable. So at the end, I would have 2 regions one of 126KB and the second of 2KB.

As my understanding, the MMU can't be used because the granularity (TSIZE 64K or 128K) is too big. So I need to use the MPU to create such region, right ? Or I'm totally wrong ?

BR,

Pat

[lukaszadrapa · Accepted solution]

Hi,

minimal size of MMU page is 1k in case of e200z4 core, so I can't see problem here:

This excel configuration tool could help:

MMU Assist Register CONFIGURATOR 

Notice that all MMU pages must be aligned. For example, 2K page must be aligned to 2K boundary, 128K page must be aligned to 128K boundary. So, if you need to create 2K page, you will need more pages to cover rest of the area.

MPU can't be used to make some area cache inhibited.

Regards,

Lukas

[Pat]

Hi lukaszadrapa‌,

OK, if I understand well we can combine several TLB of different size to make the desired granularity. In my case I need to set :

SRAM region Cacheable : 1 TLB of 64K + 1 TLB of 32K + 1 TLB of 16K + 1 TLB of 8K

SRAM region uncacheable : 1 TLB of 8K

That gives total of 128K SRAM.

BR,

Pat

[lukaszadrapa]

Yes, that's it, your understanding is correct.

Regards,

Lukas