How to Test SDADC in MPC5777C ?

[ignatiusmichael]

Hi all,

I just configured SDADC_1 and SDADC_4 to work in differential input mode and i am unable to test it correctly

My configuration -

SDADC_1
SDADC_1_MCR 00011001 PDR 00: OSR = 24
PGAN 00: Gain = 1
HPFEN 01: High-pass (DC removal) filter is enabled
WDGEN 00: WDG is disabled
TRIGEDSEL 00: Falling edge of trigger input is selected
TRIGEN 01: Trigger input is enabled
TRIGSEL 00: Input trigger 0 is selected
FRZ 00: Conversions are not stopped
VCOMSEL 00: Negative input terminal is biased with VREFN
WRMODE 00: Wraparound mechanism disabled (in this case the default software control mechanism will be enabled)
GECEN 00: Gain error calibration mode disabled
MODE 00: Differential input mode selected
EN 01: SDADC internal modulator enabled
SDADC_1_CSR 00000000 BIASEN 00
ANCHSEL_WRAP 00
ANCHSEL 00
SDADC_1_RKR 0000A50F RESET_KEY A50F
SDADC_1_SFR 00000004 ANCHSEL_CNT 00
DFEF 00: Data FIFO is not empty
WTHH 00: Watchdog Upper Threshold Cross Over Event did not occur
WTHL 00: Watchdog Lower Threshold Cross Over Event did not occur
CDVF 01: Data output from SDADC is valid
DFORF 00: No overrun has occurred since the last time the flag was cleared
DFFF 00: The number of datawords in FIFO is less than the number indicated by FCR[FTHLD]
SDADC_1_RSER 00010001 WTHDIRS 00: Interrupt request is selected
DFFDIRS 01: DMA request is selected
GDIGE 00: No impact of external gating signal on module DMA/interrupt requests
WTHDIRE 00: Interrupt/DMA request is disabled on WDG Threshold Cross Over Event
CDVEE 00: Event output disabled
DFORIE 00: Interrupt request is disabled when data FIFO overrun condition occurs
DFFDIRE 01: Interrupt/DMA request is enabled when data FIFO full condition occurs
SDADC_1_OSDR 00000001 OSD 01
SDADC_1_FCR 00000807 FRST 00: No effect
FTHLD 08
FOWEN 00: Data FIFO OW option disabled
FSIZE 03: FIFO depth = 16 datawords
FE 01: Data FIFO is enabled; FIFO depth is indicated by FSIZE
SDADC_1_STKR 00000000 ST_KEY 0000
SDADC_1_CDR 0000FFFA CDATA FFFA
SDADC_1_WTHHLR 00000000 THRH 0000
THRL 0000

SDADC_2

SDADC_3

SDADC_4
SDADC_4_MCR 00013001 PDR 00: OSR = 24
PGAN 00: Gain = 1
HPFEN 01: High-pass (DC removal) filter is enabled
WDGEN 00: WDG is disabled
TRIGEDSEL 01: Rising edge of trigger input is selected
TRIGEN 01: Trigger input is enabled
TRIGSEL 00: Input trigger 0 is selected
FRZ 00: Conversions are not stopped
VCOMSEL 00: Negative input terminal is biased with VREFN
WRMODE 00: Wraparound mechanism disabled (in this case the default software control mechanism will be enabled)
GECEN 00: Gain error calibration mode disabled
MODE 00: Differential input mode selected
EN 01: SDADC internal modulator enabled
SDADC_4_CSR 00000000 BIASEN 00
ANCHSEL_WRAP 00
ANCHSEL 00
SDADC_4_RKR 0000A50F RESET_KEY A50F
SDADC_4_SFR 00000004 ANCHSEL_CNT 00
DFEF 00: Data FIFO is not empty
WTHH 00: Watchdog Upper Threshold Cross Over Event did not occur
WTHL 00: Watchdog Lower Threshold Cross Over Event did not occur
CDVF 01: Data output from SDADC is valid
DFORF 00: No overrun has occurred since the last time the flag was cleared
DFFF 00: The number of datawords in FIFO is less than the number indicated by FCR[FTHLD]
SDADC_4_RSER 00010001 WTHDIRS 00: Interrupt request is selected
DFFDIRS 01: DMA request is selected
GDIGE 00: No impact of external gating signal on module DMA/interrupt requests
WTHDIRE 00: Interrupt/DMA request is disabled on WDG Threshold Cross Over Event
CDVEE 00: Event output disabled
DFORIE 00: Interrupt request is disabled when data FIFO overrun condition occurs
DFFDIRE 01: Interrupt/DMA request is enabled when data FIFO full condition occurs
SDADC_4_OSDR 00000001 OSD 01
SDADC_4_FCR 00000807 FRST 00: No effect
FTHLD 08
FOWEN 00: Data FIFO OW option disabled
FSIZE 03: FIFO depth = 16 datawords
FE 01: Data FIFO is enabled; FIFO depth is indicated by FSIZE
SDADC_4_STKR 00000000 ST_KEY 0000
SDADC_4_CDR 00000003 CDATA 0003
SDADC_4_WTHHLR 00000000 THRH 0000
THRL 0000

I am using the MPC5777C Evaluation Board to test it 

So to test   SDADC_1 i supplied GND to PO15 and PQ0

and to test SDADC_4 i supplied GND to PU7 and PU8

i was expecting the result to be 0 (or somewhat close to 0) but my results are just random value varying between 0 to 0xFFFF. What am i doing wrong please help

Thank you in advance

[davidtosenovjan · Accepted solution]

Hi,

here you may find simple example using potentiometer connected to PO15 and it is working fine:

https://community.nxp.com/docs/DOC-330909 

Hope it helps

[ignatiusmichael]

Thank You for your help, so i was able to figure out what i was doing wrong, i was supplying the i/p pins via the pot on the EVB and i had also enabled the High Pass filter so because of that i guess it was blocking my DC signal and i was not able to observe any o/p.