Explanation about content of SRRO AND SRR1 registers in IVOR3 Exception(MPC5748G)

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Explanation about content of SRRO AND SRR1 registers in IVOR3 Exception(MPC5748G)

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FAISAL0323
Contributor II

Hi Experts

In my NXP MPC5748G project,  I got following exception. Through debugging it is found that, contents of SRR0 and SRR1 registers are 0x00000000 and 0x01010101 respectively. Please let me know what does that information mean? How to interpret information from these registers so that we can know the cause of that exception. 

 

Does SRR1 means it will have same values as in MSR register.? If yes please let me  know which bits in MSR they are set. 

 

Furthermore Please let me know the source of that exception. Here in picture  below, it is mention this is because of Execute Access Control exception. What does it mean? I need details on that. 

 

Thanks in advance

Regards

Faisal 

FAISAL0323_0-1653554271361.png

 

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

Does SRR1 means it will have same values as in MSR register.? If yes please let me know which bits in MSR they are set.

Yes. Whole content of MSR is saved.

Zen z4204n3 core implements the EIS Volatile Context Save/Restore APU to support the capability to quickly save and restore volatile register context on entry into an interrupt handler.

When an interrupt occurs, the contents of the MSR are saved to one of the machine state save/restore registers (SRR1, CSRR1, DSRR1, MCSRR1).

Save/Restore register 1 (SRR1). The SRR1 register is used to save machine state from the MSR on non-critical interrupts, and to restore machine state when an se_rfi executes.

Furthermore Please let me know the source of that exception. Here in picture below, it is mention this is because of Execute Access Control exception. What does it mean? I need details on that.

Instruction Storage Interrupt (Offset 0x30) - Not able to read instruction from memory. Most probably it is ECC error.

Best regards,

Peter

 

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shanix
Contributor II

Hello,I got some information about ECC errors from the document Error Correction Codes Implemented on MPC5744P. In the chapter 5 it talks about e200z4 core response on ECC event. According to this document ECC event only will cause IVOR1 or IVOR4, so I want to know how ECC events cause IVOR3 (Instruction Storage interrupt) to be triggered.

Thanks.

shanix_0-1654311265828.png

 

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

To be precise for MPC5748G device below is the explanation.

petervlna_0-1654585561459.png

best regards,

Peter

 

 

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