ETimer frequency problem of MPC5744P

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ETimer frequency problem of MPC5744P

957 Views
nathan_
Contributor IV

I need to use the eTimer module of MPC5744P to measure the duty of PWM.

My relevant code is as follows:

//CLK Init

MC_CGM.AC3_SC.B.SELCTL = 0x01; //connect XOSC to the PLL0 input
MC_CGM.AC4_SC.B.SELCTL = 0x01; //connect XOSC to the PLL1 input
// Set PLL0 to 200 MHz with 40MHz XOSC reference
PLLDIG.PLL0DV.R = 0x3002100A; // PREDIV = 1, MFD = 10, RFDPHI = 2, RFDPHI1 = 6
MC_ME.RUN0_MC.R = 0x00130070; // RUN0 cfg: IRCON,OSC0ON,PLL0ON,syclk=IRC

MC_CGM.AC0_DC0.R = 0x80030000;    // MOTC_CLK : Enable aux clk 0 div by 4 ?(50 MHz)50M

//GPIO Init

SIUL2.MSCR[2].B.IBE = 1; /* PA2: Enable pad for input - eTimer0 ch2 */
SIUL2.IMCR[61].B.SSS = 2; /* eTimer0 ch2: connected to pad PA2 */

static void eTimer_Init(void)
{
ETIMER_0.ENBL.R = 0x0; // disable Timer0 channels

ETIMER_0.CH[2].CTRL1.R = 0x3802; // Counts only rising edge of the MC_CLK (100MHz in RUN0), divide by 1, count up, count repeatedly, rollover
ETIMER_0.CH[2].COMP1.R = 0xFFFF;
ETIMER_0.CH[2].CCCTRL.R = 0x0264; // compare on COMP1 when counting up, COMP2 when counting down
// CAPT2 on falling edge, CAPT1 on rising edge, 2 entries
// free-running mode
ETIMER_0.CH[2].CTRL3.R = 1;

ETIMER_0.ENBL.R = 0x0004; // Enable Timer0 channel 2

}

int main(void)
{
xcptn_xmpl (); /* Configure and Enable Interrupts */

eTimer_Init();

ETIMER_0.CH[2].CCCTRL.B.ARM = 1; // starts the input capture process

/* Loop forever */
while(1)
{
while(0x0080 & ETIMER_0.CH[2].STS.R){

capture_ch0[0] = ETIMER_0.CH[2].CAPT1.R;
capture_ch0[1] = ETIMER_0.CH[2].CAPT2.R;
capture_ch0[2] = ETIMER_0.CH[2].CAPT1.R;
capture_ch0[3] = ETIMER_0.CH[2].CAPT2.R;

edge1 = capture_ch0[0];//capture_ch1[0]*65536 + capture_ch0[0]; // save 1st rising edge
edge2 = capture_ch0[1];//capture_ch1[1]*65536 + capture_ch0[1]; // save 1st falling edge
edge3 = capture_ch0[2];//capture_ch1[2]*65536 + capture_ch0[2]; // save 2nd rising edge
edge4 = capture_ch0[3];//capture_ch1[3]*65536 + capture_ch0[3]; // save 2nd falling edge

// calculate period, pulseH, pulseL, freq and duty
if(edge3>edge1)
{
counts1 = edge3 - edge1;
}
else
{
counts1 = (0xFFFF - edge1 +1) + edge3;
}

freq = (float)50000000.0/counts1;//(float)100000000.0/counts1;
period = counts1 / (float)50000.0;

if(edge2>edge1)
{
counts2 = edge2 - edge1;
}
else
{
counts2 = (0xFFFF - edge1 +1) + edge2;
}

pulseH = counts2 / (float)50000.0;
pulseL = period-pulseH;

duty = pulseH/period*100;
ETIMER_0.CH[2].STS.R = 0x00C0; // clear eTimer0 channel 0's capture1/2 flags
SIUL2.GPDO[0].R ^= 0x1;
}
}
return 0;
}

On my demo board, a PWM of 2kHz is generate on the A[2] pin, and the result is correct;

On my controller board, as for the crystal oscillator is 10MHz, so the MC_CGM.AC0_DC0.R is changed as follows:

 MC_CGM.AC0_DC0.R = 0x80000000;    // MOTC_CLK : Enable aux clk 0 div by 1(50M)

to keep the MOTC_CLK consistent.

Then I test my controller board with the same signal.

But it turns out that the test result for the PWM is incorrect and the result varies. There is no difference but the MC_CGM.AC0_DC0.R register between the codes.

What might be the problem? Are there any hardware problem with the MPC5744P on the controller board?

 

2 Replies

633 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

in that example the MOTC_CLK is clocked from PLL0. The PLL0 was set to 200MHz running from 40MHz crystal.

If you keep that PLL0 setting and have 10MHz crystal, you will not have valid configuration.

If you need PLL0=50Mhz then use 

// Set PLL0 to 50 MHz with 10MHz XOSC reference

PLLDIG.PLL0DV.R = 0x2006101E;      // PREDIV =  1, MFD = 30, RFDPHI = 6, RFDPHI1 = 4

for 200MHz

// Set PLL0 to 200 MHz with 10MHz XOSC reference

PLLDIG.PLL0DV.R = 0x30021028;             // PREDIV =  1, MFD = 40, RFDPHI = 2, RFDPHI1 = 6

BR, Petr

633 Views
nathan_
Contributor IV

In my code, because of the following code:

PLLDIG.PLL0DV.R = 0x3002100A; // PREDIV = 1, MFD = 10, RFDPHI = 2, RFDPHI1 = 6

 

So I think with the 10MHz XOSC, the PLL0 = 10M * 10 / 2 = 50M, then I set 

MC_CGM.AC0_DC0.R = 0x80000000;    // MOTC_CLK : Enable aux clk 0 div by 1(50M)

So the MOTC_CLK is 50M

Is there any problem with my set? Or there are some limit I did not know?

Thank you.

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