I have multiple questions that I met when I read the MPC5674FRM, Application Note AN5200 and Application Note AN4513.
1 - In ECSM_ESR register part of RM, why re-reading the ECSM _ESR suggested? Is it just to be sure we read the ECSM_ESR correctly? The related figures is below;
2 - In 3.2 ECSM part of AN4513, there is information about using ECSM reporting without an interrupt is requested. I understand from this information, we can just use ECSM reporting without interrupts. (I don't want to handle the errors, I just want to know there is a problem.)
However, in 4.1 Single-bit error detection and correction Section of AN4513, I understand that if we set the R1BC and F1BR, it will result in an ECC request to the interrupt controller.
So I think there is a discrepancy. Can you give me a hand to figure out the topic?
3 - What is the meaning of "over program" which is seen in AN5200? How does writing the data B to the same flash memory location creates multiple bit ECC error?
1) It is just prescribed sequence that is needed to keep in order to have valid results. In the code it seems as follows:
/* 1. Read the ECSM_ESR and save it */
ecsm_esr = (uint8_t)ECSM.ESR.R;
/* 2. Read and save all the address and attribute reporting registers */
ecsm_rear = (uint32_t)ECSM.REAR.R;
ecsm_remr = (uint8_t)ECSM.REMR.R;
ecsm_reat = (uint8_t)ECSM.REAT.R;
/* 3. Re-read the ECSM_ESR and verify the current contents matches
the original contents. If the two values are different, go back
to step 1 and repeat */
if (ecsm_esr == (uint8_t)ECSM.ESR.R)
/* 4. When the values are identical, write a 1 to the asserted ECSM_ESR flag
to negate the interrupt request - we actually negate both flags */
ECSM.ESR.R = 0x03;
2) ECSM interrupts may not be used. But reading 2-bit affected data always reads in bus error i.e. machine check exception. This exception cannot be disabled.
3) It means program without erase in between. In the flash it creates data pattern affected by ECC error.