You have basically 2 main options:
1) either you can configure separate DMA TCD for every transfer. As for ADC there is only one DMA trigger source, these TCDs must be linked (let only last converted channel to trigger first DMA transfer) either by link feature or by scatter gather feature.
2) read the all channel data registers at once. Even in case some channels are unused, it may be easier for instance if target destination in RAM memory followed by certain SW processing.
Yes, you can use proper channel offset if gaps between converted channnel are regular i.e. you may sequentially read for example channels 0, 2, 4, 6, 8, 10, 12, 14 or 1, 3, 5, 7, 9, 11, 13, 15 or similar way. Your sequence cannot be configured by address offsets.
