Hi there,
While investigating the issues in my previous post, I discovered there may be an inconsistency in your SEMC driver when initializing the SRAM interface.
A previous user asked about the purpose of the COL field in SRAMCR0, and NXP technician Yuri advised "Bit field COL of SRAM control register 0 (SRAMCR0) is not used, may be zero." Following is the source code in the FSL SEMC driver that initializes the register (I've removed grayed-out code for clarity):
{
tempCtrlVal = SEMC_SRAMCR0_PS(config->portSize) |
SEMC_SRAMCR0_BL(config->burstLen) | SEMC_SRAMCR0_AM(config->addrMode) |
SEMC_SRAMCR0_ADVP(config->advActivePolarity) |
SEMC_SRAMCR0_COL_MASK;
}
base->SRAMCR0 = tempCtrlVal;
The issue is that SEMC_SRAMCR0_COL_MASK is 0xF000, not 0. While both 0000 and 1111 select the same COL value of 12 bits, I'm concerned that setting this field to anything other than its power-on default of 0 might introduce side effects for an unused field. I suggest changing this code to read:
{
tempCtrlVal = SEMC_SRAMCR0_PS(config->portSize) |
SEMC_SRAMCR0_BL(config->burstLen) | SEMC_SRAMCR0_AM(config->addrMode) |
SEMC_SRAMCR0_ADVP(config->advActivePolarity) |
SEMC_SRAMCR0_COL(0);
}
base->SRAMCR0 = tempCtrlVal;
There is also a similar use of the SEMC_SRAMCR0_COL_MASK macro about 14 lines prior that should also be replaced with SEMC_SRAMCR0_COL(0).
David R.
