LPC54608 configuration for LPM

[shashankpathak]

Hi,

I am trying to use deep sleep mode in LPC54608. I am using GINT0 as a wake up source and able to put the CPU in deep sleep mode  and wake up it through button connected to one of the GINT0 pin. Below is the code for it,

EnableDeepSleepIRQ(GINT0_IRQn);
uint32_t pdruncfg0 =
                        0x4                                      |
                        SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK        |
                        SYSCON_PDRUNCFG_PDEN_SRAMX_MASK          |
                        SYSCON_PDRUNCFG_PDEN_SRAM0_MASK          |
                        SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK      |
                        SYSCON_PDRUNCFG_PDEN_ADC0_MASK           |
                        SYSCON_PDRUNCFG_PDEN_VD3_MASK            |
                        SYSCON_PDRUNCFG_PDEN_VD4_MASK            |
                        SYSCON_PDRUNCFG_PDEN_VD5_MASK            |
                        SYSCON_PDRUNCFG_PDEN_VD6_MASK            ;
uint32_t pdruncfg1 = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
POWER_EnterPowerMode(kPmu_Deep_Sleep, (uint64_t)pdruncfg0 +(((uint64_t)pdruncfg1)<<32));

Now the question here is that I have to use "0x04" bit mask. The bit corresponding to it is bit 2 in PDRUNCFG0, now the reference manual for LPC54608 specifies this bit as reserved.

Is the documentation missing something?

Also, If I don't keep the ADC on during the deep sleep mode then on wake up, the ADC module remains turned off, it is not turning on when exiting deep sleep mode.

Do I need to reprogram PDRUNCFG0 on exiting of deep sleep mode to turn the required modules on?

Regards,

Shashank.

[xiangjun_rong]

Hi, Shashank,

I have checked the bit definition of PDRUNCFG0 register, the bit2 is reserved, in other worlds, it is not open to customer.

How do you know that you have to set the bit 2 of PDRUNCFG0 register?

Regarding the ADC power-down mode, if you do want to run the ADC, I suppose that you have to clear the ADC corresponding bits so that the ADC can work after exit from the low power mode.

Hope it can help you

BR

XiangJun Rong

[shashankpathak]

Hi XiangJun Rong,

My understanding of bit2 of PDRUNCFG0 register behavior was incorrect. I am now able to get proper deep sleep behavior without using the bit 2 of PDRUNCFG0 register.

Regarding the ADC, if I don't keep the ADC on during the deep sleep mode then on exit from deep sleep mode, I need to calibrate the ADC again to get the ADC working which seems expected behavior as per the reference manual.

Regards,

Shashank.