FlexSPI configuration block in MCUXpresso

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FlexSPI configuration block in MCUXpresso

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nilsl
Contributor II

How to suggest an improvment of the MCUXPresso SDK or file a pull request?
We've found that there is a slightly misleading comment in XIP-setup of the some of the EVK-boards (evkmimxrt1160 and evkmimxrt1170). A little better source code documentation would have saved us a lot of time making the i.MXRT1176 boot from FlexSPI2, Secondary Pin Group (see our found solution here).

I believe the following comment does not correspond with this setting

    // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
    .controllerMiscOption = 0x10,

  in the files evkmimxrt1160_flexspi_nor_config.c and evkmimxrt1170_flexspi_nor_config.c.

It should rather be

    // Enable Safe Configuration Frequency for devices supporting DDR Read instructions
    .controllerMiscOption = (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable),

which would produce the same code.

However, I'm unsure if this setting makes any sence, since DDR / DTR seems not to be enabled anyway to access the IS25WP128 Serial NOR chip on the two EVKs (Single Data Rate seems to be used).

In our case, it was important to set bit 8 to enable Secondary Pingroup for our custom board (a board which is otherwise heavily based on the EVK schematic and the MCUXpresso sample code for the EVK). Currently, there is no available enum-constant for "Secondary Pingroup" in the header file. I suggest adding it to MCUX SDK, for example with the name  kFLEXSPIMiscOffset_SecondPinGroup next to the above option in xxx_flexspi_nor_config.h.

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jingpan
NXP TechSupport
NXP TechSupport

Hi @nilsl ,

I guess this is because few project will use second pinmux. I'll escalate your suggestion to software team.

Here is a very good guide for use flexspi2.

https://www.arrowsolution.com.cn/index.php/Home/Detail/articles/id/183.html

 

Regards,

Jing

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application_ninja
Contributor III

This link no longer works, is there an update?

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