LPC51U68 and SRAM Memory access

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LPC51U68 and SRAM Memory access

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christian_gross
Contributor II

Hello forum,

I have 2 questions about how memory access works on the LPC51U68.

As I understand it, from looking in the User manual (UM11071 page 6 fig. 1), both the ARM core and the DMA module can access both Main SRAM and SRAMX module on the chip.

1) Is acces to each SRAM module restricted to one at a time? If the ARM core is busy wrting to Main SRAM then the DMA module have to wait to access the same Main SRAM.
2) If ARM core is accessing SRAMX, can the DMA module access the MAIN SRAM at the same time? So they are both using the AHB bus at the same time, but not accessing the same SRAM module.

Best regards.
Christian G.

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soledad
NXP Employee
NXP Employee

Hi, 

1) Yes, the access it is restricted and prioritize

2) Yes, this can be done, but as you may understand the ARM Core has privileges and priority over the DMA to avoid any conflicts. So even both can be access to different zones, the AHB would prefer the ARM core over the DMA by default.

I hope this helps, have a nice day!

Regards

Soledad

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soledad
NXP Employee
NXP Employee

Hi, 

1) Yes, the access it is restricted and prioritize

2) Yes, this can be done, but as you may understand the ARM Core has privileges and priority over the DMA to avoid any conflicts. So even both can be access to different zones, the AHB would prefer the ARM core over the DMA by default.

I hope this helps, have a nice day!

Regards

Soledad

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christian_gross
Contributor II

Hello Soledad,

Yes, that answered my question. Thank you!

Best regards.

Christian

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