Hi NXP team,
Can we remove the CPLD from the LS2088A-rdb design and all the reset and critical signal on which LS2088A boot depends, can be driven by mosfet logics.
Of course CPLD is not absolutely required for the LS2088A-based designs.
The LS2088ARDB design was implemented using CPLD just because that it was convenient for the board designer.
Other approaches also are possible considering that requirements of the processor's Data Sheet and Design Checklist are fulfilled.
we have bypassed the cpld, but at the time we are doing DDR SPD read from CW tap we are facing issue. Can you please let me know the reset sequence to be followed at this DDR SPD read from CW TAP operation.