LS1046A EP reset

[fcenedese]

Hello

We have a board with a LS1046A as PCIe endpoint. Now when the CPU hangs itself we need to make a hard reset. This will also clear out the PCIe registers with BARs and MSI data. I'm now trying to save the necessary contents to restore them after the reset so the communication with the PCIe host (PC) will continue to work.

I thought of using the OCRAM but couldn't find whether this keeps the content in a hard reset or not, first tests indicate not. Is there some other area that I can use to keep data over a hard reset or do I have to keep them off-CPU, as in a NvRam or Eeprom? Is there a better way to reset the CPU? I've seen the core soft resets, but they need the cores to still be working to be executed.

Thanks

[fcenedese]

I'm now trying to issue core soft resets, however I must be missing something as nothing happens.

// set and enable interrupt 196, edge trigger
// trigger
GICD_ICFGR[]=...
GICD_ITARGETSR[]=...
// irq's are group 1
GICD_IGROUPR[]=...
GICD_IGRPMODR[]=...
 // enable interrupt
GICD_ISENABLER[]=...

// enable soft reset
uint32* pEnable = (uint32*)0x01570204;
setbe32(pEnable, 0x80000000);
// set vector
uint32* pVector = (uint32*)0x01570220;
setbe32(&pVector[0], 0x80000000 >> 2);
// issue reset
uint32* pReset = (uint32*)0x01570130;
setbe32(&pReset[0], 0x80000000);

Do I need to set other registers as well? Is there somewhere an example?
I know that I need to provide a place to jump to where a WFI instruction is,
but the CPU never comes there, it just continues to work. I'm thinking that
writing to the register to issue the interrupt 196 may actually work but the
interrupt is pending somewhere. Where could I look if the interrupt is
actually issued and pending?

Thanks

[yipingwang]

Have you tried using the watchdog timer in order to reset the system ? Instead of doing a hard reset, you can configure the watchdog timer to automatically force a reset in case the cpu hangs.

[fcenedese]

Thanks. But we'd also like to be able to issue a reset even if the CPU is not hanging. And on the other hand an automatic reset would clear the state the CPU is in and therefore preventing us from examining what went wrong.

So what is missing in my code to issue a core reset on demand? Do you have an example?

Thanks

[yipingwang]

Discussing with the AE team.

[fcenedese]

Do you have any new information?

[yipingwang]

Have you referred to Section 4.4.3 Core Soft Reset of LS1046A RM for your implementation ? Attaching the RM just in case. Also where are you running this code, uboot or linux ?

[fcenedese]

Yes, that's the steps I followed. We use a different OS (neither u-boot nor linux), assume bare-metal.

[yipingwang]

Got it.