LS1043A -- Is this PCIE_PORT_DEBUG1 register available for LS1043A SoC?

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LS1043A -- Is this PCIE_PORT_DEBUG1 register available for LS1043A SoC?

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daweichen
Contributor III

Per one NXP's linux-qoriq (branch: lf-5.10.y) git comment, the LS1043A PCIE controller driver should use the DWC common link-up check function.  The common function reads the status from the PCIE_PORT_DEBUG1 register (at address offset 0x72C).  

I noticed Document Number: LS1043ARM Rev. 6, 07/2020 does not have this register defined. 

Could someone from NXP help clarify the discrepancy?   

I see two possibilities. 

[1] The patch is wrong because the register does not exist.

[2] The register exists but is not documented.

Thank you so much,

===

Reference [1]: the git commit

PCI: layerscape: Change to use the DWC common link-up check function · nxp-qoriq/linux@d23f0c1 · Git...

Reference [2]:  DWC common link-up check function

int dw_pcie_link_up(struct dw_pcie *pci)
{
u32 val;

if (pci->ops && pci->ops->link_up)
return pci->ops->link_up(pci);

val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
}

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yipingwang
NXP TechSupport
NXP TechSupport

I confirmed with LSDK development team.

This register exists but is not listed in LS1043ARM, you can refer to the DWC document attached.

yipingwang_0-1694484803247.png

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daweichen
Contributor III

Thank you so much for the help!

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yipingwang
NXP TechSupport
NXP TechSupport

 The iMX6 there were 2 registers at internal offset 0x728 and 0x72c called DEBUG0 and DEBUG1 respectively. Debug1, bit 4 indicated the LTSSM "link up"status. This still seems to be the case on the LS1043A, but these registers are not documented.

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daweichen
Contributor III

 

"This still seems to be the case on the LS1043A, but these registers are not documented."

<Dawei> Would you be kind enough to confirm definitively that those registers indeed exist on the LS1043A?

 

"Debug1, bit 4 indicated the LTSSM "link up"status."

<Dawei> Could you please help confirm Debug1, bit 29 indicates "link in training" status?

 

We have a PCIE module that sometimes fail to complete driver initialization due to "link in training" / "link up" status.

 

Thank you so much,

Dawei

 

Reference: NXP linx-qoriq 5.10.72

#define PCIE_PORT_DEBUG1 0x72C
#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29) 

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yipingwang
NXP TechSupport
NXP TechSupport

I confirmed with LSDK development team.

This register exists but is not listed in LS1043ARM, you can refer to the DWC document attached.

yipingwang_0-1694484803247.png