LS1028A Power Sequencing Conflict In Documentation


LS1028A Power Sequencing Conflict In Documentation

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Contributor II

I believe there is a power sequencing conflict between the LS1028A datasheet and the PMIC datasheet.

The LS1028A datasheet shows the power sequencing requirements as follows.

  • Step 1: 1.8V
  • Step 2: 1.0V / 0.9V
  • Step 3: 1.35V

The PMIC for the LS1028A (34VR500V9) shows the following sequence.

  • Step 1: 2.5V
  • Step 2: 1.8V
  • Step 3: 1.35V
  • Step 4: 1.0V / 0.9V, LDO output for VDD enable
  • Step 5: LDO output for DDR enable

The 1.35V and 1.0V (VDD) are out order between the two datasheets.

We are considering implementing a custom power scheme not utilizing the NXP PMIC. What order is correct?




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NXP TechSupport
NXP TechSupport

The power sequence described in the data sheet is correct.

Note that 'Step 3' of the power sequence contains following remark:

"System with DDR4 memory (1.2V): G1VDD (XVDD, AVDDSD1_PLL1 and AVDD_SD1_PLL2 can be powered up in any step)". In other words, 1.35V order is relaxed in DDR4 case, so no conflict.





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