LS1012A eDMA memory allocation problem

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LS1012A eDMA memory allocation problem

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Gyosun
Contributor III

Hello,

I am currently testing eDMA with the assistance of the link provided below.

https://community.nxp.com/t5/QorIQ/Request-for-LS1012A-EDMA-module-program-memory-copy-example/m-p/1...

I am testing eDMA memcpy with a small size (1024B). There are no issues when copying with intervals. However, when copying consecutively, I encounter a failure in memory allocation at the dma_pool_alloc() function within the fsl_edma_alloc_desc() function.

ex) dma_pool_alloc() fail

for (i=0;i<16384;i++)
{
  device_prep_dma_memcpy(dst, src, 1024);
  tx_submit();
  dma_async_issue_pending();
}

If you could provide any suggestions or solutions on how to increase
the memory or resolve the issue, 
I would greatly appreciate it.

Thanks,

Gyosun.

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1 Solution
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yipingwang
NXP TechSupport
NXP TechSupport

For case2:
We had tried kernel 5.10 which released in LSDK 21.08, applied the patch mentioned previously. No memory allocation issue. We thought this issue due to memory management update with kernel, no change of DMA driver. You can try to optimize driver code to fix the issue.

For case3 and 4, please modify code as below.
+ /* To match with copy_align and max_seg_size so 1 tcd is enough */
+ //fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
+ // EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE,
+ // 32, len, 0, 1, 1, 32, 0, true, true, false);
+ fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
+ EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT,
+ 1, len, 0, 1, 1, 1, 0, true, true, false);


+ //fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_32_BYTES;
+ fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_1_BYTE;

In attachment, mentioned those available data for SSIZE.

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yipingwang
NXP TechSupport
NXP TechSupport

Have you used the test case in https://community.nxp.com/t5/QorIQ/Request-for-LS1012A-EDMA-module-program-memory-copy-example/m-p/1...
If yes, then you should increase the allocation buff size.
Currently the size was defined as: uint32_t buf_size = 4*1024*1024;

After changing the size, if you still face issue, please send us the related code,
so that we can reproduce your issue.

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Gyosun
Contributor III

Hi yipingwang,

Thank you for your response.
I tried changing the buf_size, but it didn't improve the situation. It seems unrelated.
I have modified the code to make it testable and attached the test logs.

https://drive.google.com/file/d/1tGMlRBzavU0SFzYH2cPzeJvTd2xXapU8/view?usp=drive_link 

In addition to the questions you asked, I have a few more inquiries.
I have assigned functions for each test case in the provided test code to facilitate issue identification.
TEST CASE1 - Original normal test
TEST CASE2 - Memory allocation issue
TEST CASE3 - Data byte alignment issue
TEST CASE4 - Address byte alignment issue

Thank you in advance.

gyosun.

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yipingwang
NXP TechSupport
NXP TechSupport

Two suggestions:
1. Please add below debug (an example) info after device_prep_dma_memcpy(dst, src, 1024); in the main.c file
if (!tx_desc) {
pr_err("[%d]Failed to prepare DMA memcpy\n", __LINE__);
return -1;
}

2. please add debug info in this function in driver to check if this function had been called.
fsl_edma_free_desc in file drivers/dma/fsl-edma-common.c
Also please check is there any operation in the dmatest.c file.

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Gyosun
Contributor III

Hi yipingwang,

Thank you for your response.

1. The code you provided has already been applied.

2. The changes were implemented in the kernel code, and I confirmed that the logs are being output.

Due to the log output, there is a delay, and the CASE2 TEST passed.

It seems that the memory allocation speed is faster than the deallocation speed, leading to memory allocation failures.

You may need to either increase the allocated memory or speed up the deallocation process, but I am unable to find a solution at the moment.

static void fsl_edma_free_desc(struct virt_dma_desc *vdesc)
{
struct fsl_edma_desc *fsl_desc;
int i;

fsl_desc = to_fsl_edma_desc(vdesc);
pr_info("%s]%d, n_tcds=%d\n", __func__,__LINE__,fsl_desc->n_tcds);
for (i = 0; i < fsl_desc->n_tcds; i++)
dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd,
fsl_desc->tcd[i].ptcd);
kfree(fsl_desc);
}

...

[ 114.743300] fsl_edma_free_desc]295, n_tcds=1
[ 114.747579] fsl_edma_free_desc]295, n_tcds=1
[ 114.751858] fsl_edma_free_desc]295, n_tcds=1
[ 114.756163] fsl_edma_free_desc]295, n_tcds=1
[ 114.760446] fsl_edma_free_desc]295, n_tcds=1
[ 114.764726] fsl_edma_free_desc]295, n_tcds=1

...

I'd appreciate it if you could review the code, and please also check CASE 3 and CASE 4.

Thanks,

gyosun.

 

 

 

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yipingwang
NXP TechSupport
NXP TechSupport

We checked the logs, some finding:

For case2:

due to below function:

fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool,

                                        GFP_NOWAIT, &fsl_desc->tcd[i].ptcd); This function return NULL due to no continuous dma memory can to be assigned.

for case3 and 4:

DMA memcpy required size and address align, so case3 and case4 failed.

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Gyosun
Contributor III

Hi yipingwang,

For case2:

Yes, that's right.
I asked for help in resolving the issue of contiguous DMA memory allocation failures.
Is there no solution for this problem?

For case 3 and 4:

Do size and address not support byte alignment?

The fsl_edma_probe() code has the following parts,

fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_32_BYTES;

fsl_edma_prep_memcpy() also has the following code.
fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE,
32, len, 0, 1, 1, 32, 0, true, true, false);

Even if you modify the above codes,
is it still impossible to resolve byte alignment for size and address?

Thanks,
gyosun.

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yipingwang
NXP TechSupport
NXP TechSupport

For case2:
We had tried kernel 5.10 which released in LSDK 21.08, applied the patch mentioned previously. No memory allocation issue. We thought this issue due to memory management update with kernel, no change of DMA driver. You can try to optimize driver code to fix the issue.

For case3 and 4, please modify code as below.
+ /* To match with copy_align and max_seg_size so 1 tcd is enough */
+ //fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
+ // EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE,
+ // 32, len, 0, 1, 1, 32, 0, true, true, false);
+ fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
+ EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT,
+ 1, len, 0, 1, 1, 1, 0, true, true, false);


+ //fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_32_BYTES;
+ fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_1_BYTE;

In attachment, mentioned those available data for SSIZE.

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Gyosun
Contributor III

Hi yipingwang,

You're the best.
Thank you for providing accurate help.

For case2:
I am currently testing with LSDK21.08 update.
Since there seems to be an issue with porting, I will ask my question on another thread.

For case3 and 4:
The problem has been resolved.

Thanks,

Gyosun.

 

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