LS1012A Serdes options

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LS1012A Serdes options

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victor0123
Contributor I

In my PCB,LS1012A Serdes lane A:SGMII1,lane B:SGMII2,lane D:PCIE(Endpoint).

SRDS_PRTCL_S1 RCW[128:143]=3305.

SD1_REF_CLK1_P/N PIN is provided 100Mhz from X86 DEMO.

The PCIE of X86 DEMO is configured to operate as a PCI Express Root Complex.

LS1012A is configured to operate as a Endpoint device.

But <QorIQ LS1012A Reference Manual  >Page 234

victor0123_0-1640835261838.png

Setting this bit to 0 is only supported with
SerDes protocol option (SRDS_PRTCL_S1) =
0x0005 ?

SGMII1 and SGMII2 can not work?

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ufedor
NXP Employee
NXP Employee

Technically SGMII should work in the described case, but configuration in question was not validated during LS1012A silicon bring-up.

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ufedor
NXP Employee
NXP Employee

Proper operation of SGMII1 and SGMII2 cannot be guaranteed when LS1012A SerDes reference clock is provided by a PCIe RC because spread-spectrum can be used.

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victor0123
Contributor I

Thanks for your reply.

If the 100Mhz reference clock provided by a PCIe RC is not a spread-spectrum,SGMII can work,right?

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ufedor
NXP Employee
NXP Employee

Technically SGMII should work in the described case, but configuration in question was not validated during LS1012A silicon bring-up.

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