IFC Latency

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 
2,378件の閲覧回数
m_syed_ahmed
Contributor III

Hi,

I am working in the LS1021 processor. we have a microcontroller (LPC4312) connected to the IFC bus. IFC will have proper data when a particular GPIO pin is toggled. MicroController makes that GPIO high when it is ready to send data and makes that GPIO low once it completes sending of data. After GPIO became low only, we can read proper data.

I need to know is there any latency in IFC where we can delay reading for some time until that GPIO goes high and low?

Also, is it possible to modify IFC read-write functions with additionally checking for that GPIO too? If yes, where exactly are IFC read-write functions are implemented?

ラベル(2)
0 件の賞賛
1 解決策
2,224件の閲覧回数
Bulat
NXP Employee
NXP Employee

No, the LS1021A does not support such huge delays in hw.

You need to change read method, e.g. poll in software for GPIO bit ready state, then read the data.

 

元の投稿で解決策を見る

0 件の賞賛
9 返答(返信)
2,371件の閲覧回数
Bulat
NXP Employee
NXP Employee

IFC supports so called "external access termination", this is similar to what you are looking for. See section 24.7.1.1.2 of the LS1021A Reference Manual for writes, section 24.7.1.2.2 for reads.

Regards,

Bulat

 

0 件の賞賛
2,356件の閲覧回数
m_syed_ahmed
Contributor III

Hi Bulat,

Sorry for the delayed response. Can you share documents or anything which explains external access termination in IFC?

I needs to know where in the linux BSP, IFC read write functions will be implemented as part of source code?

Also, is it possible to assign different IFC clocks for different connected IFC devices? It seems micro controller needs to be set lower IFC clock for it to catch IFC bus signals properly?

0 件の賞賛
2,339件の閲覧回数
Bulat
NXP Employee
NXP Employee

IFC GPCM read/write operations (including external termination) do not require any software support from BSP.

IFC external termination is descrobed in the ref manual, I already provided direct references in the document.

IFC clock is common for all connected devices.

 

 

0 件の賞賛
2,332件の閲覧回数
m_syed_ahmed
Contributor III

Hi Bulat,

We were worried that the microcontroller which is running in the lower frequency is not able to capture IFC signals which were running in higher frequency. Is there anything we can do through software wise to resolve it?

0 件の賞賛
2,320件の閲覧回数
Bulat
NXP Employee
NXP Employee

IFC clock is scalable via IFC_CCR[CLKDIV].

0 件の賞賛
2,258件の閲覧回数
m_syed_ahmed
Contributor III

Hi Bulat,

We did the IFC clock scaling through the CCR register. we set that as divisible by 8. We also set the IFC FTIM registers as low as possible (1). We need to hold OE and CS for at least a 1-second delay before assertion for Controller to process read operation. It seems those signals were held up in nanoseconds only.  Is there something we need to change in software to hold those signals for 1 second?

0 件の賞賛
2,225件の閲覧回数
Bulat
NXP Employee
NXP Employee

No, the LS1021A does not support such huge delays in hw.

You need to change read method, e.g. poll in software for GPIO bit ready state, then read the data.

 

0 件の賞賛
2,196件の閲覧回数
m_syed_ahmed
Contributor III

What could be the highest delay possible in GPCM OE signals? Also, did FC_CCR impact OE assertion time as IFC_FTIM1 do?

0 件の賞賛
2,139件の閲覧回数
Bulat
NXP Employee
NXP Employee

OE signal assertion time is defined by FTIM_1[TRAD]. This does not depend on the CCR[CKLKDIV] clock ratio.

0 件の賞賛