Dear All,
I am using LS1012A-FRWY and it has Winbond SPI flash w25q16dw.
Currently QSPI flash is set for 1-4-4 (EB) instruction. I want to enable QPI instruction 4-4-4. I have read in specification that we need to fire 38h instruction but I am not sure how to enable it. Can anyone guide me how to enable QPI from Kernel or u-boot source code?
Thanks.
Solved! Go to Solution.
here is reply from IP owner.
There is no significant improve to switch from 1-4-4 Quad SPI Instruction to 4-4-4 QPI instruction, compare the overhead and payload, QPI may only save 6 clock cycles per ~300 clock cycles, in AHB read mode.
So it’s only around 2% improvement.
If customer do need to run in 4-4-4 mode, they can refer to micron_st_nor_octal_dtr_enable() function in drivers/mtd/spi-nor/micron-st.c file, it shows how to set register bit and enable QPI/OPI mode.
I checked the source code, it seems there is spi_nor_micron_octal_dtr_enable() function had been added from kernel 5.15.
static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor, bool enable) {
struct spi_mem_op op;
u8 *buf = nor->bouncebuf;
int ret;
if (enable) {
/* Use 20 dummy cycles for memory array reads. */
ret = spi_nor_write_enable(nor);
if (ret)
return ret;
*buf = 20;
op = (struct spi_mem_op)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1),
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_OUT(1, buf, 1));
ret = spi_mem_exec_op(nor->spimem, &op); ....
Thank you for answer.
here is reply from IP owner.
There is no significant improve to switch from 1-4-4 Quad SPI Instruction to 4-4-4 QPI instruction, compare the overhead and payload, QPI may only save 6 clock cycles per ~300 clock cycles, in AHB read mode.
So it’s only around 2% improvement.
If customer do need to run in 4-4-4 mode, they can refer to micron_st_nor_octal_dtr_enable() function in drivers/mtd/spi-nor/micron-st.c file, it shows how to set register bit and enable QPI/OPI mode.
I checked the source code, it seems there is spi_nor_micron_octal_dtr_enable() function had been added from kernel 5.15.
static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor, bool enable) {
struct spi_mem_op op;
u8 *buf = nor->bouncebuf;
int ret;
if (enable) {
/* Use 20 dummy cycles for memory array reads. */
ret = spi_nor_write_enable(nor);
if (ret)
return ret;
*buf = 20;
op = (struct spi_mem_op)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1),
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_OUT(1, buf, 1));
ret = spi_mem_exec_op(nor->spimem, &op); ....