Do I need IEEE 1588 Synchronous connection to a Quad PHY for a TSN application?

[Sbayley]

Hello,

We are are implementing a design with TSN ethernet capabilities with the LS1028A acting as the TSN switch. The LS1028A connects to a Quad PHY (BCM54140B0IFBG). The Quad PHY has a connection for a synchronous 1PPS input. Do I need to implement the IEEE 1588 clock generation to synchronize these two? We are generating the input clocks for the LS1028A Serdes block and the input clock to the Quad PHY from the same clock generator to keep the clock signals as in sync as possible? So do I still need this dedicated IEEE 1588 clock signal to synchronize the two chips?

Thank you,

Sean

[Sbayley]

Hi Yipingwang,

Thank you for your response.

We are using the BCM54140B0IFBG as our Quad PHY.

So am I understanding correctly that you are suggesting the following? :

We should connect a clock from our clock generator to the input clock option on the ethernet controller block (pin AD2 on the LS1028A). We will need to select this clock as the input for the 1588 timer with register TMR_CTRL(CLK_SEL).

Then we will need to connect one of the SWITCH_1588_DATn signals (such as AH4 on the LS1028A) as the clock pulse signal to the PHY sync line?

Is that correct?

Regards,

Sean Bayley

[yipingwang]

We should connect a clock from our clock generator to the input clock option on the ethernet controller block (pin AD2 on the LS1028A). We will need to select this clock as the input for the 1588 timer with register TMR_CTRL(CLK_SEL).
[NXP: ]Yes, this is correct regarding the requirement of LS1028A for 1588.
EC1_1588_PULSE_OUT1 (AG5) is 1PPS of LS1028A 1588 timer. This signal will be connected to Quad PHY tigger_in/1PPS_in signal

I will not be able to comment on PHY sync line input. Please refer to its data sheet.

[yipingwang]

Time synchronization using IEEE 1588 PTP can occur both at the MAC level within the LS1028A and at the PHY level.
I don't have specific information about the PHY's role in Time-Sensitive Networking (TSN), please share PHY's datasheet for more insights into its involvement in the process.

In order to utilize 1588 time synchronization at the MAC level on the LS1028A, customer will need to take the following steps:
1. Connect the input clock of the 1588 timer from the clock generator. (We are generating the input clocks for the LS1028A Serdes block and the input clock to the Quad PHY from the same clock generator)
2. Connect 1PPS of LS1028A 1588 timer to Quad PHY tigger_in/1PPS_in signal