I have a custom LS1046A board with some discrete DDR4 devices on it. I'm attempting to perform the QCVS DDR validation on it. It is currently configured with an RCW and PBI, the PBI sets up the DDR registers.
For the Centering the clock test, the first part of the test passes (Auto search & detect for write leveling start values).
All subsequent parts of the test fail as "D_INIT was not cleared by hardware", and the ACE bit in 0xE40 is set.
Some of the CLK_ADJ fail with "Invalid value at 0xF04: 0x00001102", and the ACE bit in 0xE40 is set. Once 1 of the tests has given this error, all following CLK_ADJ tests also give this error, but the test that gives it first is not consistent.
Once it has run to completion, if I attempt to re-run the whole procedure, the first part of the test (Auto search & detect for write leveling start values, which had previously passed) fails with the error: "Write Leveling start values are correct and require no further modification, but the test failed due to other issues.", and once again the ACE bit in 0xE40 is set.
In fact, in order to get it to pass on the first part of the test again, I have to power cycle the board. After which, the first part passes and then all subsequent parts fail again.
What would cause it to pass first time but fail afterwards? How might I get it to pass on the subsequent runs?
Just in case anyone else has this issue;
The problem turned out to be the SDRAM reset logic. When the CPU asserts HRESET, the SDRAM reset also needs to be asserted. I had the same logic driving both resets, but HRESET wasn't able to drive the SDRAM reset.