I am in the process of laying out the DDR4 interface for our LS1028A application and had a couple of questions related to the AN5097 checklist.
The last bullet on No. 27 states: "For 32-bit or 16-bit DDR4 data bus, the bit 0 (DQ[0]) and bit 1 (DQ[1]) of ECC
byte lane, bit-swap is not allowed." My initial interpretation of this is that bit 0 and bit 1 of the ECC's data bus cannot be bit-swapped. However, the reference design board has the following bit swapped interface:
DQ0->D1_MECC3
DQ1->D1_MECC1
DQ2->D1_MECC2
DQ3->D1_MECC0
I would like to implement the following bit-swapping order for Rank 1:
DQ0->D1_MECC2
DQ1->D1_MECC0
DQ2->D1_MECC3
DQ3->D1_MECC1
...and this order for Rank 2:
DQ0->D1_MECC0
DQ1->D1_MECC2
DQ2->D1_MECC1
DQ3->D1_MECC3
Is this bit swap permitted? I do not understand this rule.
My second question relates to No. 25 in the checklist, specifically this statement: "Spacing >= 2-3x distance from signal to adjacent ground plane in PCB stack-up". Is this the trace to trace spacing? If so, is it center-to-center or edge-to-edge?
