Hi,
Regarding the AOREG1 register, as the section 13.4.13, the AOREG1 register is " managed and updated by the ROM Boot Code.",after each reset, the boot code is re-executed, the AOREG1 register is updated once based on different Reset source.
The waking up from deep power down will reset the processor and the processor will re-execute the Boot code and update the AOREG1 register.
The Watch Dog reset will reset the processor and the processor will re-execute the Boot code and update the AOREG1 register.
The System Reset" (SYSTEMRESET) or a "Pin Reset" (PADRESET) will reset the processor and the processor will re-execute the Boot code and update the AOREG1 register.
The PoR, Brown Out Detectors Reset will reset the processor and the processor will re-execute the Boot code and update the AOREG1 register. The POR means that the power-up process will generate the POR reset. The Brown Out Detectors Reset means that when the VBAT_DCDC voltage is less than a threshold voltage, it generate BOD interrupt or reset, but your firmware has to be configured to generate BOD reset.
I copy it from UM11126.pdf
4.6.4 Brown-out detection
This device includes one Brown-out detector to monitor the voltage of VBAT. If the voltage
falls below one of the selected voltages, see Section 13.4.6 “VBAT Brown Out Detector
(BoD) control register” the BOD asserts an interrupt to the NVIC or issues a reset, see
Section 13.4.1 “Power Management Controller FSM (Finite State Machines) status
(STATUS)”.
The interrupt signal can be enabled for interrupt in the interrupt enable register in the
NVIC, see Table 8 to cause a CPU interrupt; if not, software can monitor the signal by
reading a dedicated status register.
If the BOD interrupt is enabled, the BOD interrupt can wake up the chip from a reduced
power mode, not including power-down and deep power-down. See Chapter 14
“LPC55S6x/LPC55S2x/LPC552x Power Profiles/Power Control API”.
If the BOD reset is enabled, the forced BOD reset can wake up the chip from reduced
power modes, not including power-down and deep power-down.
I copy it from UM11126.pdf
13.4.13 General purpose always on domain data storage
This register is managed and updated by the ROM Boot Code. It gathers some important
System Status information like the last System reset cause and the number of fatal errors
that occurred during the ROM boot. Though it is readable and writable, it can not be
modified by any application.
Hope it can help you
BR
XiangJun Rong
