UM10973 documentation error regarding JP6

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UM10973 documentation error regarding JP6

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cyanic
Contributor I

Looking at the schematic for LPCXpresso54114, it seems by default the nOE pin of the transceiver is pulled low (i.e. enabled), and only pulled high if JP6 is fitted. However in the manual for the board, it says "JP6 needs to be fitted to use the SPI bridging function between the LPC54114 and Link2." which actually isolates the connection. I'm assuming this is an error?

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Cyanic,

As the following schematics, if the JP6 jumper is closed, the /OE pin of 74AVC4TD245BQ will be high, the 74AVC4TD245BQ output will be disabled, the SPI of link side and the spi of LPC54114 side can not communicate.

When JP6 jumper is open, the /OE pin of 74AVC4TD245BQ will be low in default because of pull-down resistor, the 74AVC4TD245BQ output will be enabled, the SPI of link side and the spi of LPC54114 side can communicate.

So I agree with you that it is wrong "JP6 needs to be fitted to use the SPI bridging function between the LPC54114 and Link2".

Hope it can help you'

BR

XiangJun Rong

xiangjun_rong_0-1634517100937.png

 

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Cyanic,

As the following schematics, if the JP6 jumper is closed, the /OE pin of 74AVC4TD245BQ will be high, the 74AVC4TD245BQ output will be disabled, the SPI of link side and the spi of LPC54114 side can not communicate.

When JP6 jumper is open, the /OE pin of 74AVC4TD245BQ will be low in default because of pull-down resistor, the 74AVC4TD245BQ output will be enabled, the SPI of link side and the spi of LPC54114 side can communicate.

So I agree with you that it is wrong "JP6 needs to be fitted to use the SPI bridging function between the LPC54114 and Link2".

Hope it can help you'

BR

XiangJun Rong

xiangjun_rong_0-1634517100937.png

 

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