Register and Memory address, Not to confuse

[lpcware]

Content originally posted in LPCWare by Verilog7777 on Sun Feb 22 00:06:34 MST 2015
Little confused about register versus memory address.
In LPC17xx manual,  UM10360.pdf page 57, the following is stated [color=#009]"Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 -
0x400F C1A8 and PCLKSEL1 - 0x400F C1AC"[/color]
Also in the beginning of the section its mentioned
[color=#009]"Each Register is 32 bits wide and byte, half-word, and word addressable"[/color]
Also from hardware standpoint, each registers are made of Flip Flops and have memory.

Question
Does that mean that Peripheral Clock Selection
Registers 0 which is called PCLKSEL0 is 32 bits wide and starting address is at 0x400F C1A8 and each address is a byte wide
and
Register 1 which is called PCLKSEL1 is 32 bits wide and starting address is at 0x400F C1AC and each address is a byte wide.

Does it mean that since each address is a byte wide, there are 4 addresses that make a register?

[lpcware]

Content originally posted in LPCWare by Verilog7777 on Sun Feb 22 03:25:03 MST 2015
Thanks R2D2. That clears this up.
That is the reason why the increment of each address is 4 bytes or 32 bits (4 bytes concatenated) which is the width of each register in the System Memory and Peripheral Map of the LPC1758;16KB address blocks allocation in APB0, APB1 .

[lpcware]

Content originally posted in LPCWare by Verilog7777 on Sun Feb 22 03:24:59 MST 2015
Thanks R2D2. That clears this up.
That is the reason why the increment of each address is 4 bytes or 32 bits (4 bytes concatenated) which is the width of each register in the System Memory and Peripheral Map of the LPC1758;16KB address blocks allocation in APB0, APB1 .

[lpcware]

Content originally posted in LPCWare by R2D2 on Sun Feb 22 02:13:33 MST 2015
See: http://en.wikipedia.org/wiki/Endianness