LPC5536 DAC problem

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LPC5536 DAC problem

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SilentBob
Contributor I

Hello,

I try to create own configuration routine for DAC0 of LPC5536. I derive the configuration routine from the driver example "lpcxpresso55s36_dac_1_basic".

Now I encountered the following problem. In a code line of my configuration routine

PMC->PDRUNCFGCLR1 = PMC_PDRUNCFG1_PDEN_DAC0_MASK;                       // 0b - DAC0 is powered

 

the debug session crashes.

vit1.png

 

Unfortunately I can't find the error. In the driver example there is not this problem.

void DAC0_init(void)

{

       uint32_t tmp32 = 0U;

       LPDAC_Type *base = DAC0;

 

       /* Set IP Clock Divider */

       SYSCON->DAC[0].CLKDIV = SYSCON_DAC_CLKDIV_RESET_MASK;                   // reset DAC

       SYSCON->DAC[0].CLKDIV = SYSCON_DAC_CLKDIV_DIV(0U);                      // DIV=1

       /* Clock Selection for IP */

       SYSCON->DAC[0].CLKSEL = SYSCON_DAC_CLKSEL_SEL(0U);                      // select main clock

       /* Disable DAC0 power down */

       PMC->PDRUNCFGCLR1 = PMC_PDRUNCFG1_PDEN_DAC0_MASK;                       // 0b - DAC0 is powered

       /* Enable the clock. */

       SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_DAC0_MASK;         // Enables the clock for DAC0.

       /* Reset the logic. */

       base->RCR |= LPDAC_RCR_SWRST_MASK;                  // Resets all DAC registers and internal logic.

       base->RCR &= ~LPDAC_RCR_SWRST_MASK;                 // Remains set until cleared by software.

       /* Reset the FIFO. */

       base->RCR |= LPDAC_RCR_FIFORST_MASK;          // Resets the FIFO pointers and flags in register FSR.

       base->RCR &= ~LPDAC_RCR_FIFORST_MASK;         // Remains set until cleared by software.

 

       tmp32 |= LPDAC_GCR_BUF_SPD_CTRL_MASK;        // Enable low power.

       tmp32 |= LPDAC_GCR_LATCH_CYC(0U);                   // The recommended sync time is at least 40ns. (25MHz => 40ns)

       tmp32 |= LPDAC_GCR_IREF_PTAT_EXT_SEL(1U);    // External PTAT current reference selected

       tmp32 |= LPDAC_GCR_DACRFS(0U);                       // VREFH1 = VDDA supply rail

//     tmp32 |= LPDAC_GCR_BUF_EN_MASK;               // Opamp is used as buffer. (Disable for fast settling time)

       tmp32 |= LPDAC_GCR_DACEN_MASK;                       // Enable the DAC hardware system

       base->GCR = tmp32;

       base->FCR = LPDAC_FCR_WML(0U);                       // Watermark Level for FIFO

 

 

       /* Reset DAC0 */

//     SYSCON->PRESETCTRLSET[0] = SYSCON_PRESETCTRL0_DAC0_RST_MASK;

//     SYSCON->PRESETCTRLCLR[0] = SYSCON_PRESETCTRL0_DAC0_RST_MASK;

}

 

void DAC0_setData(uint32_t value)

{

       LPDAC_Type *base = DAC0;

       base->DATA = LPDAC_DATA_DATA(value);

}

Please can someone help me to find the problem?

 

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1 Reply

427 Views
Alice_Yang
NXP TechSupport
NXP TechSupport

Hello,

How about debug DAC demo under SDK?  

 

 

 

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