LPC5460x Vector Table Offset Register VTOR

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LPC5460x Vector Table Offset Register VTOR

Contributor II


  I'm writing a bootloader to be used with an LPC54607J256ET180E.  In the LPC546xx User manual, UM10912, Rev. 2.4 — 11 November 2019, section 6.2 on page 71 references the existence of a Vector table offset register VTOR.  The remaining 1,181 pages in that document make no further mention of this register other than to note in section 42.3, paragraph 3, that re-mapping the vector table is possible.  Presumably it relocates the vector table from FLASH to RAM but without documentation I can't perform the relocation as would be required when switching from the bootloader to the runtime code.  Other LPC-family components have similar registers.  For example, the LPC13xx has a SYSMEMREMAP register at 0x4004 8000 which has two bits to relocate the vectors to either boot ROM, RAM, or FLASH.  Where in memory is the VTOR register on the LPC546xx and what is the definition of its bits?  Thanks for filling in the gaps in the published documentation.



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NXP TechSupport
NXP TechSupport

Hello Andrew,

There is a bootloader application, you can refer to, it includes how to use VTOR:






Senior Contributor II

The VTOR register is not vendor-specific, but part of the common core the NXP MCUs share with all other Cortex M devices. Setup and behavior are thus identical on all parts (at least M3 and M4).

I suggest the technical reference manual from ARM as literature, like here: https://developer.arm.com/documentation/100166/0001

Other vendors rely on ARM for core-specific information the same way. Albeit some years ago, NXP still duplicated a lot of this information in specific MCU manuals.