LPC3141, CS High to OE High Timing Question

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LPC3141, CS High to OE High Timing Question

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StanleyH
NXP Employee
NXP Employee

Hi Support team,

  We have a question about the timing specification in the LPC3141 datasheet. Need some explanation.

Please refer the tCSHOEH specification in the SRAM controller module as below. The minimum requirement is 3ns. However our typical is 0ns. Seems strange. Is the data correct? If yes, can you please give some explanation. Thanks.

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-Customer, Delta IABU.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Stanley,

Regarding your question, I have consulted with engineer in AE team, we think it is a typo, it should be -3ns instead of 3ns.
The spec tCSHOEH is the time from CS HIGH to OE HIGH, when the rising edge of OE signal is before the rising edge of CS signal, it is a negative value. It can explain why the minimum is 3, typical is 0. In other words, it should be:
minimum     typical
-3ns            0
Hope it can help you.

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1,244 次查看
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Stanley,

Regarding your question, I have consulted with engineer in AE team, we think it is a typo, it should be -3ns instead of 3ns.
The spec tCSHOEH is the time from CS HIGH to OE HIGH, when the rising edge of OE signal is before the rising edge of CS signal, it is a negative value. It can explain why the minimum is 3, typical is 0. In other words, it should be:
minimum     typical
-3ns            0
Hope it can help you.

1,243 次查看
StanleyH
NXP Employee
NXP Employee

Hi X.J,

  Thanks a lot for the reply.

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