CAN base address align restriction in LPC55

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CAN base address align restriction in LPC55

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javiervallori
Contributor III

Hi,

I recently post a question because I had a rare RAM problem. Finally I realized that the reason of the problem came from the need to align the CAN0_RAM_BASE_ADDRESS to 0x10000.

The CAN0_RAM_BASE_ADDRESS is linked into the .bss section. By default in the linker_file.ld automate generated by the MCUxpresso, the .bss output section comes after the .data output section, and both are linked into the RAM_0_1_2 (0x20000000). This RAM has a lenght of 0x10000.

So, if .data is not empty, CAN0_RAM_BASE_ADDRESS can not be linked into the address 0x20000000 because it is already use by .data vars, and the following address aligned to 0x10000, is 0x20010000, and unfortunetly is out of range of the RAM_0_1_2.

This restricion make quiet unuseful the CAN module using CAN_MSG_RAM_BASE, because any static var initialization will cause a compilation error due to RAM out of range fail.

I found a workaround, using a manual .ld file and puting the .data after the .bss, but I don't like pretty much.

In my opinion this CAN module has a very big restriction with the alignment and the range memory of this microcontroler, and is something that should be take in consideration in following developments.

This post is just to help someone that have had the same problem, and to open a discousion about it findig a better solution.

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ZhangJennie
NXP TechSupport
NXP TechSupport

This problem will be fixed in SDK 2.11.0 Major Release.

Thank you for bringing the problem to our attention!

Best Regards

Jun Zhang

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ZhangJennie
NXP TechSupport
NXP TechSupport

This problem will be fixed in SDK 2.11.0 Major Release.

Thank you for bringing the problem to our attention!

Best Regards

Jun Zhang

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ValentinCh
Contributor I

Hi,

I'm facing the same issue.
I've downloaded the 2.11 SDK and the bug does not seem to have been fixed.
(I need to put the bss section before the data section)

Do you have any updates ?

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javiervallori
Contributor III

Hi Valentin,

I get an alternative workaround from NXP, maybe more simple because it is just a small code change in the peripheral.c file. They propouse to add a forced CAN_MESSAGE_RAM initialization avoiding to put it in the .bss.

 

SDK_ALIGN(uint32_t CAN0_RAM_BASE_ADDRESS[CAN0_MESSAGE_RAM_SIZE], CAN0_BASE_ADDRESS_ALIGN_SIZE) = {1};

I hope it helps.

 

 

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ValentinCh
Contributor I

I will go with it ! I didn't think about this workaround.

Thank you !

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