Content originally posted in LPCWare by FutureDesign on Fri Feb 06 07:50:47 MST 2015 We are developing a battery operated LPC1788 device that has a LCD, SDRAM, NOR FLASH, UART and touch controller. During the idle state the system has to go to low power mode to preserve the battery. Among all the devices we find some issues while bringing down the SDRAM to power down state.
As I understand, there is a particular type of CKE signal transition that has to be synchronous with clock that takes the SDRAM device into power down mode. The user manual of the LPC1788 explains about the method of SDRAM low power mode. It is available in Rev 3 user manual on page 179, section 9.6.1.
The section of the user manual says to set DP, CS and CE bit of EMDDynamicControl register.
However, in LPC1788 EMC register description there is a register called " Dynamic Memory Control Register" that contains CS and CE bit but there is no DP bit.
Investigating on ARM resources we found out that bit # 13 of the DynamicControl register is the DP bit. But Bit # 13 of that register in LPC1788 is labeled as reserved.
Even though it is labeled as reserved, we tried to set these bits and we seems to be able to bring SDRAM in power down mode. But the LCD DE signal disappears after clearing back the DP bit in order to use the SDRAM and hence the LCD does not work. During many trial, LCD worked few times but we could not understand why it does not work and rarely works. SDRAM seems to be working fine after DP bit is cleared.
* Is it valid to use the DP bit in LPC1788? If so why it disturbs the LCD functionality. Is there any way out for this? * If DP bit is not suggested for use, then what is the method by which we can take the external SDRAM in power down mode.
Content originally posted in LPCWare by FutureDesign on Tue Feb 10 06:49:55 MST 2015 Hi,
Thanks for the reply. The CPU is properly going to deep power down mode and properly coming up. Actually without DP bit being touched, it was working well. But we want to save more power. After few more tests it is observed that when the DP bit is set the SDRAM immediately goes to low power shutdown mode. On other side, the LCD engine was still working and it was trying to access the SDRAM for frame buffer. May be there was some LCD DMA access error that we could not track. And after waking up, the LCD was not working. Even after re -initializing LCD module it does not work. LCD worked only after POR.
We disabled the LCD module by clearing Enable bit in LCd module control register and wait about 200 mSec before setting the DP bit in EMC. This resolved the problem. If we remove 200mSec delay, LCd does not after wake up. But again why 200 mSec delay? If we lower this sometime the LCD gets stuck like before. Is there any way to ensure the DMA of LCD is completely stopped ? So that we can monitor and once it is stopped the DP bit in EMC can be cleared.
Content originally posted in LPCWare by xianghuiwang on Mon Feb 09 15:20:05 MST 2015 Hi, We will confirm the background to mark bit 13 as reserved in EMCDynamicControl register. For your low power mode operation, have you tried to put the chip to deep sleep or power down mode? Make sure you reconfigure the PLL after waking up if used before entering deep sleep or power down mode. Please reference AN11096 for the low power mode usage of this part. http://www.lpcware.com/content/nxpfile/an11096-using-lpc178x7x-power-modes-software regards,