How to receive arbitrary number of bytes through SPI DMA (Kinetis SDK)?

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How to receive arbitrary number of bytes through SPI DMA (Kinetis SDK)?

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aamartir
Contributor I

Hi,

 

I have a KS22 controller that is configured as a SPI slave device. Another microcontroller (SPI Master) wishes to send some arbitrary number of bytes (not much, maybe 15 to 200 bytes at a time). Now, I've configured the KS22 to use SPI over DMA and noticed that I have to define how much data I wish to send/receive in order for the DMA interrupt to trigger. This is not ideal for me since I don't know how much data the Master is going to send beforehand.

 

My question is, without having to provide some kind of handshake (meaning, the Master having to send some pre-defined header before the actual data), how can the KS22 slave device receive arbitrary number of bytes using the SPI DMA provided code (Kinetis SDK)?  I notice that whenever the Master de-asserts the Chip Select line, the SPI Slave does not interrupt. What I would like is for the Slave to provide a big enough receive buffer (256 bytes should be enough for my application). As soon as either the buffer gets full, or Chip Select is de-asserted, the low layer SPI DMA should interrupt me. Is this possible with the current Kinetis SDK?

 

Thank you for taking the time to read through this post.

 

Alex

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Alex,

If you do not know the size of data the master would transfer in advance for the SPI slave side, I suggest you use the example

C:\Freescale\SDK2.0_FRDM_K22F\boards\frdmk22f\driver_examples\dspi\interrupt\kds

In the example, each received data will trigger interrupt, you can read it to a buffer in the ISR.

If you use DMA mechanism, you have to define the size of data you transmitted or received, so that the DMA can trigger interrupt when size of buffer has been transferred completely, this is DMA essence.

For the /SS signal  of SPI, the /SS pin becomes low when the transfer is in progress for each byte/half-word transfer generally, when each transfer is over, the /SS is high.

Hope it can help you

BR

Xiangjun Rong

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