What is the bus clock frequency range for ADC on Kinetis K12 (MK12DN512)

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

What is the bus clock frequency range for ADC on Kinetis K12 (MK12DN512)

Jump to solution
1,505 Views
DeepakKukreja
Contributor III

Hi,

On the MK12DN512VLK5 Kinetis K12 part, what is the clock frequency range for the ADC. The reference manual mentions in couple of places that the ADC clock frequency should be in the specified range but I could not find the actual frequency specification.

#kinetis_12‌, #adc clock frequency

1 Solution
1,418 Views
kerryzhou
NXP TechSupport
NXP TechSupport

Hi Deepak Kukreja,

  Which ADC clock source you are using now?

pastedImage_1.png

If you are using the ADACK, it is in the datasheet:

pastedImage_2.png

pastedImage_3.png

pastedImage_4.png

Best Regards,

Kerry

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

View solution in original post

3 Replies
1,419 Views
kerryzhou
NXP TechSupport
NXP TechSupport

Hi Deepak Kukreja,

  Which ADC clock source you are using now?

pastedImage_1.png

If you are using the ADACK, it is in the datasheet:

pastedImage_2.png

pastedImage_3.png

pastedImage_4.png

Best Regards,

Kerry

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

1,418 Views
DeepakKukreja
Contributor III

Hi kerryzhou,

Thanks for sharing the relevant portions from the Reference Manual.

From the snapshots of the reference manual, does it imply that only the ADACK needs to meet the specifications, and there is no such restrictions in case bus clock is used as the input clock?

I am planning on using the bus clock, and will be trying with the below options:

Can you please validate my calculations below:

OPTION 1: Bus clock (48 MHz) with no divider, fastest conversion

ADCx_CFG1[ADICLK] set to 0(dec). Input clock set to bus clock

ADCx_CFG1[ADIV]   set to 0(dec). Divide ratio is 1

I assume ADCK gets set to 48 MHz

OPTION 2: Bus clock(48 MHz)/2 with max. divider, slowest conversion

ADCx_CFG1[ADICLK] set to 1(dec). Input clock set to bus clock/2

ADCx_CFG1[ADIV]   set to 3(dec). Divide ratio is set to 8

I assume ADCK gets set to 3 MHz

I have another query regarding the conversion time calculation, but I will create a separate query for that

Thanks

0 Kudos
Reply
1,418 Views
kerryzhou
NXP TechSupport
NXP TechSupport

Hi Deepak Kukreja ,

  Other clock, you need to meet the conversion clock requirement:

8.jpg

Any new questions, welcome to create the new question post.

Best Regards,

Kerry

 

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------