Has anyone measured the current in the VLLS(1,2,3) modes? I am measuring across the J8 jumper on the K60N512 Tower module and have measured roughly ~.68mA for all VLLS modes. The specification for the K60N512 says the power should be much lower, I was just wondering if this is an impact of the Tower module or maybe the specification is incorrect?
Also, I have been unable to successly reset out of the VLLS modes. When I press the reset (SW3) button, the software does not restart correctly. I have tried unmasking the ACKISO bit in the LLWS_CS during code startup, but that hasnt helped. I also am assuming the SW3 button triggers the RESET on the K60N512. Any suggestions???
There are some aspects you need to take into consideration when entering the low power modes in order to achieve the power consumption figure depicted in the datasheet, unfortunately it is somehow extensive thus it is not mentioned in the datasheet, however you can find all necessary considerations and steps in AN4470:
You can also find the code example in our website as AN4470SW.
Did you check the errata for this mode, I know that some of the low power modes are impacted on the current revision of silicon.
I also met the problem that MCU is halted, reset function did not work well since the reset button was pushed. The LED D2 of TWRK60N512 slightly brights even if after I tun off and turn on power of board. Voltage on pin reset_b of MCU was measured ~1.5V.
I have found in Errata sheet, the statement e2613 indicated that it may related to VLLS mode and guide me to "Exiting from VLLS modes requires that VDD be less than 2.0 V". However I dont'now how to do this, and I not sure my board problem is the problem related to VLLS mode or not.
Please to help.
Hi, have you found the solution to your problem? I think I am in the same situation and I don't know how to solve it!