TWR-K70 DDR Controller

[AnEngineer]

Hi together,

I have the TWR-K70 development Board together with the TWR-SER board. Aftrer successfully implemented the CAN Interface, I would like to use the 1GB onboard DDR memory. Regarding to the datasheet, there is a 1GB DDR memory of the type MT47H64M16 on the board. So I started the freescale tool to generate the initialisation file for this kind of memory.

When integrating it into my project, the project hangs up, and even the debugger crashes.

Perhaps there is still something wrong regarding to the different clock settings. I am using the clock setup "1" out of the file "system_MK70F12.c":

1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
         Reference clock source for MCG module is an external reference clock source 50MHz
         Core clock = 120MHz, BusClock = 60MHz

#elif (CLOCK_SETUP == 1)
    #define CPU_XTAL0_CLK_HZ                50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
    #define CPU_XTAL1_CLK_HZ                8000000u  /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
    #define CPU_XTAL32k_CLK_HZ              32768u    /* Value of the external 32k crystal or oscillator clock frequency in Hz */
    #define CPU_INT_SLOW_CLK_HZ             32768u    /* Value of the slow internal oscillator clock frequency in Hz  */
    #define CPU_INT_FAST_CLK_HZ             4000000u  /* Value of the fast internal oscillator clock frequency in Hz  */
    #define DEFAULT_SYSTEM_CLOCK            120000000u /* Default System clock value */

#elif (CLOCK_SETUP == 1)
  /* SIM_SCGC5: PORTA=1 */
  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=5,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM->CLKDIV1 = (uint32_t)0x01350000UL; /* Update system prescalers */
  /* SIM_SOPT2: PLLFLLSEL=1 */
  SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~0x00020000UL) | (uint32_t)0x00010000UL); /* Select PLL 0 as a clock source for various peripherals */
  /* SIM_SOPT1: OSC32KSEL=0 */
  SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
  /* SIM_SCGC1: OSC1=1 */
  SIM->SCGC1 |= (uint32_t)0x20UL;
  /* PORTA_PCR18: ISF=0,MUX=0 */
  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
  /* Switch to FBE Mode */
  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  OSC0->CR = (uint8_t)0x80U;
  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  OSC1->CR = (uint8_t)0x80U;
  /* MCG_C7: OSCSEL=0 */
  MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
  MCG->C2 = (uint8_t)0x20U;
  /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  MCG->C1 = (uint8_t)0xAAU;
  /* MCG_C4: DMX32=0,DRST_DRS=0 */
  MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */
  MCG->C5 = (uint8_t)0x04U;
  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */
  MCG->C6 = (uint8_t)0x08U;
  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
  MCG->C11 = (uint8_t)0x00U;
  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
  MCG->C12 = (uint8_t)0x00U;
  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
  }
  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  }
  /* Switch to PBE Mode */
  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */
  MCG->C6 = (uint8_t)0x48U;
  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  }
  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */
  }
  /* Switch to PEE Mode */
  /* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  MCG->C1 = (uint8_t)0x2AU;
  while((MCG->S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
  }

What other possibilities can I check to get the controller working?

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[AnEngineer]

Ok, so I solved my problem!

The problem was, that the PLL1 was not setup.

Adding (C10) and modifying (C11, C12) these lines got the controler working:

MCG->C10 = (uint8_t)0x14;
MCG->C12 = (uint8_t)0x0EU;
MCG->C11 = (uint8_t)0x44U;

[apanecatl]

Nice to hear you solved the issue :smileygrin:!!

[AnEngineer]

I checked the code you sent to me.

Unfortunately the behavior is exactly the same as before. The system hangs and the debugger crashes.

The debugger crashes at the following line:

SIM->MCR &= 0xFFFFFF00;

The message is: Could not stop Cortex-M device. Please checkt the jtag cable.

Regarding the cable and the debugger everything is ok. I can debug other projects very well.

[apanecatl]

I find it a bit weird since the SIM_MCR register does not contain any configuration register that could cause the debugger to lose connection, the trace clk signal is only used along with the data tracing lines which I assume you are not using, and even if the trace clock is disabled it does not cause the debugger to lose connection, only from responding to the trace commands. Unless you were already executing code from the DDR memory and then modified the memory type which could cause the application to crash but that is not the case.

[AnEngineer]

Ok. I checked it once again. It seems you are right.

The debugger crashes a few lines later on:

DDR->CR00 = 0x00000400;    // DDRCLS, start

"Cannot access target. Shutting down debug session."

I can cause these reaktion either in debugging in flash or in debugging in RAM.

[apanecatl]

I don't think the problem is related to the k70's MCG configuration, I think it might be related to the DDR configuration. You can find the the TWR-K70F120M DDR chip configuration in the file below, compare it to your configuration code to make sure it's correct.

[AnEngineer]

Hey, thanks for your answer.

I used the output generated by the freescale tool, as already mentioned.

Comparing it to your code, I found differences for the CR21 and CR53,54,56. Could you explain me?

I will check the code you offered on Monday!

[apanecatl]

There is a known issue for the K70 DDR configuration tool, in some cases it will generate erroneous values for DDR configuration registers CR9, CR21, CR53, CR54 and CR56, in these cases those registers must be written manually with the correct values which must be calculated according to the information depicted in the Reference Manual. The file I sent you has the correct configuration and it is used in an example code, that is why I asked you to compare it to the file you obtained using the tool.