Pin migration between K21_50 MHz and K21_120 MHz devices in the 121-MAPBGA package

[michaelgoudey]

I am considering pin migration between 50MHz and 120MHz K21 devices in the 121-MAPBGA packages.  It appears the 120MHz device pinout is a superset in many ways so shared features should be available with a single board design.  There are a couple of questions though:

(1) K21_120 includes an extra VDD/VSS pair in the 121-MAPBGA package.  These are NC pins on the K21_50 device.  How should I design a board to accommodate both devices?  Can the NC pins be connected to VDD/VSS for the 50MHz device?

(2) Are there any considerations for clocking to support both devices?  I realize FEI (FLL-Enabled Internal) mode won't accommodate 120MHz operation, so I believe I should populate an external crystal.  Is there any preference for frequency?

Thanks,

Michael Goudey

[Hui_Ma · Accepted solution]

Hi Michael,

1> The NC pins means there is no connection with internal die. There without any problem to connect VDD/VSS to those NC pins for the 50MHz device.

2> Both devices PLL and FLL using the same reference clock frequency. The oscillator support clock frequency is totally same. For running MCG in PEE mode, Customer can select 8MHz crystal.

Have a great day,
best regards,

Ma Hui

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