Kinetis K20 uP hangs if allowed to power down to 1.81V, then power reapplied

[Trilliant-K20]

If power removed, wait for caps to drain, at critical 1.81V (just above 1.80V spec Vmin), then power reapplied, k20 uP never comes back up running, appears to be "hung". Cannot use our PE Micro JTAG in this case, because it loses power (debug session dies) when we get down into 1.81V range. In order to get K20 back up & running, have to remove power and allow Vin to drop < 1.80V (i.e. hard reset), then once power reapplied, K20 comes up running fine.

Is there any known errata (couldn't find any) or some other cause (K20 internal peripheral component) for K20 to hang in this specific scenario. We hit this condition on very rare occasion in field after power glitch.

thanks.

[xiangjun_rong]

Hi,

The K20 has LVD module, which monitor the VDD voltage.

For detailed inf, pls refer to section 15.3 Low-voltage detect (LVD) system in RM of K20.

As a workaround, when the VDD voltage is less than a programmable threshold, you can have the LVD to generate LVD Reset.

You can also has the LVD to generate interrupt when the VDD voltage is less than a programmable threshold, in the ISR of LVD, you can generate system reset with the code.

SCB->AIRCR|=1<<2;

or call

__NVIC_SystemReset();

__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)

{

__DSB(); /* Ensure all outstanding memory accesses included

buffered write are completed before reset */

SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

SCB_AIRCR_SYSRESETREQ_Msk);

__DSB(); /* Ensure completion of memory access */

for(;;) /* wait until reset */

{

__NOP();

}

}

I copy from RM of K20.

15.3 Low-voltage detect (LVD) system
This device includes a system to guard against low-voltage conditions. This protects
memory contents and controls MCU system states during supply voltage variations. The
system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user-

selectable trip voltage: high (VLVDH) or low (VLVDL). The trip voltage is selected by the
LVDSC1[LVDV] bits. The LVD is disabled upon entering VLPx, LLS, and VLLSx
modes.
Two flags are available to indicate the status of the low-voltage detect system:
• The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF
bit is set when the supply voltage falls below the selected trip point (VLVD). The
LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal
supply has returned above the trip point; otherwise, the LVDF bit remains set.
• The low voltage warning flag (LVWF) operates in a level sensitive manner. The
LVWF bit is set when the supply voltage falls below the selected monitor trip point
(VLVW). The LVWF bit is cleared by writing one to the LVWACK bit, but only if
the internal supply has returned above the trip point; otherwise, the LVWF bit
remains set.
15.3.1 LVD reset operation
By setting the LVDRE bit, the LVD generates a reset upon detection of a low voltage
condition. The low voltage detection threshold is determined by the LVDV bits. After an
LVD reset occurs, the LVD system holds the MCU in reset until the supply voltage rises
above this threshold. The LVD bit in the SRS register is set following an LVD or poweron
reset.
15.3.2 LVD interrupt operation
By configuring the LVD circuit for interrupt operation (LVDIE set and LVDRE clear),
LVDSC1[LVDF] is set and an LVD interrupt request occurs upon detection of a low
voltage condition. The LVDF bit is cleared by writing one to the LVDSC1[LVDACK]

Hope it can help you

BR

XiangJun Rong

[Trilliant-K20]

NXP engineer,

    Can you please verify I am setting up for LVD Reset. With below code, we are not seeing an LVD Reset to occur. If it is occurring, we do not know, because the board never comes back up running after a power cycle with specific timing to cause board (uP) to hang.

//Generate a MCU LVD RESET, not an LVD interrupt, at LVDH trip point.

LVD_InitCircuit(void)
{
...

PMC_LVDSC1 = PMC_LVDSC1_LVDV(0x1); /* LVDV=1 (LVDH Trip Point), LVDIE=0, LVDRE = 0 */
PMC_LVDSC1 |= PMC_LVDSC1_LVDRE_MASK;

PMC_LVDSC2 = 0; /* LVWV=0 (Low Trip Point), LVWIE = 0 */
.....

Where:

PMC_LVDSC1_LVDRE_MASK = 0x10 = b4 = 1 = LVDRE bit

[xiangjun_rong]

Hi,

When the K20 starts up, it monitors the VDD voltage and generates POR(Power On Reset) when VDD power supply voltage rises from GND to 3.3V.

But When the VDD is less than 1.8V, the K20 can not run in the power supply voltage, when you connect 3.3V, because the VDD is greater than the POR threshold voltage, the POR circuit can not generate POR reset, so the K20 can not start-up in the case.

I suppose the K20 can start-up if you press reset pin.

Hope it can help you

BR

XiangJun Rong

[Trilliant-K20]

What is the POR threshold voltage?

[Trilliant-K20]

I see in K20 data sheet,

Symbol Description                                  Min. Typ. Max.
VPOR   Falling VDD POR detect voltage 0.8 1.1 1.5 V

Data sheet doesn't supply a detailed explanation for VPOR. Can you explain in more detail please. Does this mean voltage must drop below 0.8 - 1.5V before POR circuit will reset K20? What voltage (min) must then be detected for K20 to start running again? Is it any voltage above 1.5V or just anything above 1.8V or has to get all the way back up to 3.3V before K20 will start running again?

[xiangjun_rong]

Hi,

As you said that in data sheet of K20, VPOR Falling VDD POR detect voltage 0.8V(min) 1.1V(typical) 1.5 V(max), it means that in the VDD falling process, the power on Reset event will happens if the VDD is less than typical  threshold 1.1V, but the threshold voltage ranges from 0.8V to 1.5V, typical is 1.1V.

In other words, when the VDD is less than 0.8V, the power on Reset event is guaranteed to happen, which also means that you can start up from the 0.8V VDD  voltage.

Hope it can help you

BR

XiangJun Rong

[Trilliant-K20]

Hi XiangJun Rong,

    This means K20 uP has a vulnerability to get into hung state any time VDD drops from 3.3V into 1.8V > VDD > 0.8V range, followed by VDD returning to 3.3V. This is a very real world potential for occurring in the field due to temporary power outages, brown outs, etc.... NXP surely must not have such a vulnerability in K20 uP. Can you tell me what is workaround (PCB layout, circuitry, etc...) to avoid or recover from this scenario?

thanks,

Dan Phillips

[Trilliant-K20]

Thank you for your reply XiangJun Rong. You have partially answered my question. Are you saying K20 uP can effectively get bricked in the field? Surely this is not the case. A deployed unit in the field cannot have its reset button pressed. What is the proper workaround to prevent this scenario from occurring? Does NXP recommend a certain board layout (signals, components) to prevent this scenario from occurring? Thank you. Dan

[Trilliant-K20]

Anyone ever experience something similar?