I am entering vlls0 in my application. Right before this I am enabling 3 external pin wakeup sources. All my wakeup sources will exit and cause a reset but upon reset the LLWU_Fx registers are not indicating any wakeup source and when I enable the LLWU isr I am not getting to my ISR. Strangely though, when I put a long delay at the beginning of my main loop before any initialization, the LLWU_Fx flag is being set and it will go to the ISR.
This will not go to my ISR:
void main(void)
{
Initialization();
DisableInterrupts;
enable_irq(LLWU_irq_no);
EnableInterrupts;
while(1){..........}
}
This will go to my ISR:
void main(void)
{
for(x=0;x<1000000;x++);
Initialization();
DisableInterrupts;
enable_irq(LLWU_irq_no);
EnableInterrupts;
while(1){..........}
}
Any assistance would be appreciated.
Hi Tarik,
Actually the strange part is that you are able to enter the LLWU ISR waking up from VLLS0 mode. The LLWU ISR is only entered when you wake up from LLS mode, all the VLLSx modes follow the reset flow. If you need to determine the pin that caused the exit of the VLLSx mode i recommend you to do the following:
There are some drivers and examples on how to do it in the KL26_SC sample code.
I tried to replicate your issue unsuccessfully. Let me know if you need me to send the code I developed in IAR for test this case.
Saludos
Santiago Lopez -- Connectivity and IoT
I am checking the RCM on startup … if (RCM_SRS0 & RCM_SRS0_WAKEUP_MASK){…} to see if the LLWU occurs and toggle a debug line. I am entering VLLS0 and when I get the external pin wakeup the chip goes through the reset sequence. The flag in the RCM registers are not being set, instead I am getting the LOCKUP bit set in the RCM_SRS1 register. What would cause this bit to be set?
The Lockup reset is caused (according with the Reference Manual Chapter 6.2.2.9 Lockup reset (LOCKUP)) by the core being locked because of an unrecoverable exception following the activation of the processor's built in system protection hardware.
It means that you have some piece of code in your software that is making the CPU to lock (access to a forbidden memory location for example). You need to check what your CPU is doing before falling into this condition.
I'm attaching the code I used for testing. It was written on IAR 7.30.1 and can be found in the path FRDM-KL26Z_SC_Rev_1.0\klxx-sc-baremetal\build\iar\kl26_llwu_validation. Give it a try and let me know if it worked for you.
Saludos
Santiago Lopez -- Connectivity and IoT
The chip is in the VLLS0 state when the reset occurs.
Hi Tarik,
What code flow are you following upon wakeup? are you trying to set some GPIO? You mention this in your last post:
am checking the RCM on startup … if (RCM_SRS0 & RCM_SRS0_WAKEUP_MASK){…} to see if the LLWU occurs and toggle a debug line
Please make sure that you are enabling the PORT clock gating before modifying the PORTx registers, this can cause the LOCKUP reset.
PD: On a previous post I mentioned
Actually the strange part is that you are able to enter the LLWU ISR waking up from VLLS0 mode. The LLWU ISR is only entered when you wake up from LLS mode, all the VLLSx modes follow the reset flow.
I forgot to mention that if you enable the LLWU interrupt without clearing the LLWU_Fx first, you will actually enter into the LLWU ISR. Maybe that's why you were entering into the interrupt after reset in the first place.
Saludos
Santiago Lopez -- Connectivity and IoT